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Partially merge r223648, r223648 and r223949 from gem(4):

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- Consistently use the newly introduced sc_mac_rxcfg throughout the driver
  instead of reading the old content of CAS_MAC_RX_CONF.
- Increment if_iqdrops instead of if_ierrors in case of RX buffer allocation
  failure.
- According to the Cassini datasheet the RX MAC should also be disabled in
  cas_setladrf() before changing its configuration.
- Add error messages to gem_disable_{r,t}x() and take advantage of these
  throughout the driver instead of duplicating their functionality all over
  the place.
This commit is contained in:
Marius Strobl 2011-07-12 13:22:17 +00:00
parent 5ed0b95417
commit 5f8a9ae4a9
2 changed files with 42 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

86
sys/dev/cas/if_cas.c
View File

@ -759,7 +759,7 @@ cas_reset_rx(struct cas_softc *sc)
* Resetting while DMA is in progress can cause a bus hang, so we
* disable DMA first.
*/
cas_disable_rx(sc);
(void)cas_disable_rx(sc);
CAS_WRITE_4(sc, CAS_RX_CONF, 0);
CAS_BARRIER(sc, CAS_RX_CONF, 4,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
@ -771,7 +771,7 @@ cas_reset_rx(struct cas_softc *sc)
((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0));
CAS_BARRIER(sc, CAS_RESET, 4,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) {
if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX, 0)) {
device_printf(sc->sc_dev, "cannot reset receiver\n");
return (1);
}
@ -786,7 +786,7 @@ cas_reset_tx(struct cas_softc *sc)
* Resetting while DMA is in progress can cause a bus hang, so we
* disable DMA first.
*/
cas_disable_tx(sc);
(void)cas_disable_tx(sc);
CAS_WRITE_4(sc, CAS_TX_CONF, 0);
CAS_BARRIER(sc, CAS_TX_CONF, 4,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
@ -798,7 +798,7 @@ cas_reset_tx(struct cas_softc *sc)
((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0));
CAS_BARRIER(sc, CAS_RESET, 4,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) {
if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_TX, 0)) {
device_printf(sc->sc_dev, "cannot reset transmitter\n");
return (1);
}
@ -813,7 +813,10 @@ cas_disable_rx(struct cas_softc *sc)
CAS_READ_4(sc, CAS_MAC_RX_CONF) & ~CAS_MAC_RX_CONF_EN);
CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
return (cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0));
if (cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0))
return (1);
device_printf(sc->sc_dev, "cannot disable RX MAC\n");
return (0);
}
static int
@ -824,7 +827,10 @@ cas_disable_tx(struct cas_softc *sc)
CAS_READ_4(sc, CAS_MAC_TX_CONF) & ~CAS_MAC_TX_CONF_EN);
CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
return (cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0));
if (cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0))
return (1);
device_printf(sc->sc_dev, "cannot disable TX MAC\n");
return (0);
}
static inline void
@ -987,7 +993,6 @@ cas_init_locked(struct cas_softc *sc)
cas_init_regs(sc);
/* step 5. RX MAC registers & counters */
cas_setladrf(sc);
/* step 6 & 7. Program Ring Base Addresses. */
CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_HI,
@ -1132,23 +1137,20 @@ cas_init_locked(struct cas_softc *sc)
/* step 11. Configure Media. */
/* step 12. RX_MAC Configuration Register */
v = CAS_READ_4(sc, CAS_MAC_RX_CONF) & ~CAS_MAC_RX_CONF_STRPPAD;
v |= CAS_MAC_RX_CONF_EN | CAS_MAC_RX_CONF_STRPFCS;
CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 0);
CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0))
device_printf(sc->sc_dev, "cannot configure RX MAC\n");
CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v);
v = CAS_READ_4(sc, CAS_MAC_RX_CONF);
v &= ~(CAS_MAC_RX_CONF_STRPPAD | CAS_MAC_RX_CONF_EN);
v |= CAS_MAC_RX_CONF_STRPFCS;
sc->sc_mac_rxcfg = v;
/*
* Clear the RX filter and reprogram it. This will also set the
* current RX MAC configuration and enable it.
*/
cas_setladrf(sc);
/* step 13. TX_MAC Configuration Register */
v = CAS_READ_4(sc, CAS_MAC_TX_CONF);
v |= CAS_MAC_TX_CONF_EN;
CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 0);
CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
if (!cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0))
device_printf(sc->sc_dev, "cannot configure TX MAC\n");
(void)cas_disable_tx(sc);
CAS_WRITE_4(sc, CAS_MAC_TX_CONF, v);
/* step 14. Issue Transmit Pending command. */
@ -1742,7 +1744,7 @@ cas_rint(struct cas_softc *sc)
/* Pass it on. */
(*ifp->if_input)(ifp, m);
} else
ifp->if_ierrors++;
ifp->if_iqdrops++;
if ((word1 & CAS_RC1_RELEASE_HDR) != 0 &&
refcount_release(&rxds->rxds_refcount) != 0)
@ -1838,7 +1840,7 @@ cas_rint(struct cas_softc *sc)
/* Pass it on. */
(*ifp->if_input)(ifp, m);
} else
ifp->if_ierrors++;
ifp->if_iqdrops++;
if ((word1 & CAS_RC1_RELEASE_DATA) != 0 &&
refcount_release(&rxds->rxds_refcount) != 0)
@ -2330,8 +2332,8 @@ cas_mii_statchg(device_t dev)
* the Cassini+ ASIC Specification.
*/
rxcfg = CAS_READ_4(sc, CAS_MAC_RX_CONF);
rxcfg &= ~(CAS_MAC_RX_CONF_EN | CAS_MAC_RX_CONF_CARR);
rxcfg = sc->sc_mac_rxcfg;
rxcfg &= ~CAS_MAC_RX_CONF_CARR;
txcfg = CAS_MAC_TX_CONF_EN_IPG0 | CAS_MAC_TX_CONF_NGU |
CAS_MAC_TX_CONF_NGUL;
if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
@ -2340,17 +2342,9 @@ cas_mii_statchg(device_t dev)
rxcfg |= CAS_MAC_RX_CONF_CARR;
txcfg |= CAS_MAC_TX_CONF_CARR;
}
CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 0);
CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
if (!cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0))
device_printf(sc->sc_dev, "cannot disable TX MAC\n");
(void)cas_disable_tx(sc);
CAS_WRITE_4(sc, CAS_MAC_TX_CONF, txcfg);
CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 0);
CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0))
device_printf(sc->sc_dev, "cannot disable RX MAC\n");
(void)cas_disable_rx(sc);
CAS_WRITE_4(sc, CAS_MAC_RX_CONF, rxcfg);
v = CAS_READ_4(sc, CAS_MAC_CTRL_CONF) &
@ -2408,6 +2402,7 @@ cas_mii_statchg(device_t dev)
v |= CAS_MAC_XIF_CONF_FDXLED;
CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, v);
sc->sc_mac_rxcfg = rxcfg;
if ((sc->sc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
(sc->sc_flags & CAS_LINK) != 0) {
CAS_WRITE_4(sc, CAS_MAC_TX_CONF,
@ -2522,23 +2517,21 @@ cas_setladrf(struct cas_softc *sc)
CAS_LOCK_ASSERT(sc, MA_OWNED);
/* Get the current RX configuration. */
v = CAS_READ_4(sc, CAS_MAC_RX_CONF);
/*
* Turn off promiscuous mode, promiscuous group mode (all multicast),
* and hash filter. Depending on the case, the right bit will be
* enabled.
* Turn off the RX MAC and the hash filter as required by the Sun
* Cassini programming restrictions.
*/
v &= ~(CAS_MAC_RX_CONF_PROMISC | CAS_MAC_RX_CONF_HFILTER |
CAS_MAC_RX_CONF_PGRP);
v = sc->sc_mac_rxcfg & ~(CAS_MAC_RX_CONF_HFILTER |
CAS_MAC_RX_CONF_EN);
CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v);
CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_HFILTER, 0))
device_printf(sc->sc_dev, "cannot disable RX hash filter\n");
if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_HFILTER |
CAS_MAC_RX_CONF_EN, 0))
device_printf(sc->sc_dev,
"cannot disable RX MAC or hash filter\n");
v &= ~(CAS_MAC_RX_CONF_PROMISC | CAS_MAC_RX_CONF_PGRP);
if ((ifp->if_flags & IFF_PROMISC) != 0) {
v |= CAS_MAC_RX_CONF_PROMISC;
goto chipit;
@ -2584,7 +2577,8 @@ cas_setladrf(struct cas_softc *sc)
hash[i]);
chipit:
CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v);
sc->sc_mac_rxcfg = v;
CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v | CAS_MAC_RX_CONF_EN);
}
static int cas_pci_attach(device_t dev);

2
sys/dev/cas/if_casvar.h
View File

@ -196,6 +196,8 @@ struct cas_softc {
u_int sc_rxcptr; /* next ready RX completion */
u_int sc_rxdptr; /* next ready RX descriptor */
uint32_t sc_mac_rxcfg; /* RX MAC conf. % CAS_MAC_RX_CONF_EN */
int sc_ifflags;
};