cxgbe: Do a more thorough job in the CLEAR_STATS ioctl.
MFC after: 3 days
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5bb17208d7
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601fce8879
@ -5492,12 +5492,56 @@ t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
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rc = read_i2c(sc, (struct t4_i2c_data *)data);
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break;
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case CHELSIO_T4_CLEAR_STATS: {
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int i;
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u_int port_id = *(uint32_t *)data;
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struct port_info *pi;
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if (port_id >= sc->params.nports)
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return (EINVAL);
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/* MAC stats */
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t4_clr_port_stats(sc, port_id);
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pi = sc->port[port_id];
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if (pi->flags & PORT_INIT_DONE) {
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struct sge_rxq *rxq;
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struct sge_txq *txq;
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struct sge_wrq *wrq;
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for_each_rxq(pi, i, rxq) {
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#if defined(INET) || defined(INET6)
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rxq->lro.lro_queued = 0;
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rxq->lro.lro_flushed = 0;
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#endif
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rxq->rxcsum = 0;
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rxq->vlan_extraction = 0;
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}
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for_each_txq(pi, i, txq) {
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txq->txcsum = 0;
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txq->tso_wrs = 0;
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txq->vlan_insertion = 0;
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txq->imm_wrs = 0;
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txq->sgl_wrs = 0;
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txq->txpkt_wrs = 0;
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txq->txpkts_wrs = 0;
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txq->txpkts_pkts = 0;
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txq->no_dmamap = 0;
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txq->no_desc = 0;
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}
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#ifdef TCP_OFFLOAD
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/* nothing to clear for each ofld_rxq */
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for_each_ofld_txq(pi, i, wrq) {
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wrq->tx_wrs = 0;
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wrq->no_desc = 0;
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}
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#endif
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wrq = &sc->sge.ctrlq[pi->port_id];
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wrq->tx_wrs = 0;
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wrq->no_desc = 0;
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}
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break;
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}
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default:
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