cxgbe(4): Deal with compressed error vectors.
MFC after: 3 days Sponsored by: Chelsio Communications
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565e916002
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@ -227,7 +227,7 @@ struct tp_params {
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uint32_t vlan_pri_map;
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uint32_t vlan_pri_map;
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uint32_t ingress_config;
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uint32_t ingress_config;
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uint32_t rx_pkt_encap;
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__be16 err_vec_mask;
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int8_t fcoe_shift;
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int8_t fcoe_shift;
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int8_t port_shift;
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int8_t port_shift;
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@ -8020,12 +8020,17 @@ int t4_init_tp_params(struct adapter *adap)
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read_filter_mode_and_ingress_config(adap);
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read_filter_mode_and_ingress_config(adap);
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/*
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/*
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* For T6, cache the adapter's compressed error vector
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* Cache a mask of the bits that represent the error vector portion of
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* and passing outer header info for encapsulated packets.
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* rx_pkt.err_vec. T6+ can use a compressed error vector to make room
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* for information about outer encapsulation (GENEVE/VXLAN/NVGRE).
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*/
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*/
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tpp->err_vec_mask = htobe16(0xffff);
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if (chip_id(adap) > CHELSIO_T5) {
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if (chip_id(adap) > CHELSIO_T5) {
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v = t4_read_reg(adap, A_TP_OUT_CONFIG);
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v = t4_read_reg(adap, A_TP_OUT_CONFIG);
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tpp->rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
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if (v & F_CRXPKTENC) {
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tpp->err_vec_mask =
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htobe16(V_T6_COMPR_RXERR_VEC(M_T6_COMPR_RXERR_VEC));
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}
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}
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}
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return 0;
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return 0;
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@ -2014,7 +2014,7 @@ struct cpl_rx_pkt {
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#define S_T6_COMPR_RXERR_VEC 0
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#define S_T6_COMPR_RXERR_VEC 0
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#define M_T6_COMPR_RXERR_VEC 0x3F
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#define M_T6_COMPR_RXERR_VEC 0x3F
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#define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_LEN)
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#define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC)
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#define G_T6_COMPR_RXERR_VEC(x) \
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#define G_T6_COMPR_RXERR_VEC(x) \
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(((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC)
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(((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC)
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@ -1808,7 +1808,7 @@ t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
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M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]);
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M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]);
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m0->m_pkthdr.flowid = be32toh(rss->hash_val);
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m0->m_pkthdr.flowid = be32toh(rss->hash_val);
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if (cpl->csum_calc && !cpl->err_vec) {
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if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) {
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if (ifp->if_capenable & IFCAP_RXCSUM &&
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if (ifp->if_capenable & IFCAP_RXCSUM &&
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cpl->l2info & htobe32(F_RXF_IP)) {
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cpl->l2info & htobe32(F_RXF_IP)) {
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m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
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m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
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