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Remove code under PMAP_CACHE_VIVT that is not compiled anymore.

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This is for ARMv4/ARMv5 and it doesn't belong in ARMv6 code.

Reviewed by:	ian
This commit is contained in:
rpaulo 2014-04-05 18:13:28 +00:00
parent 0160f80f72
commit 60abae8fbc
3 changed files with 0 additions and 15 deletions
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6
sys/arm/arm/cpufunc_asm_arm11.S
View File

@ -44,12 +44,6 @@ __FBSDID("$FreeBSD$");
* addresses that are about to change. * addresses that are about to change.
*/ */
ENTRY(arm11_setttb) ENTRY(arm11_setttb)
#ifdef PMAP_CACHE_VIVT
stmfd sp!, {r0, lr}
bl _C_LABEL(armv5_idcache_wbinv_all)
ldmfd sp!, {r0, lr}
#endif
mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */

5
sys/arm/arm/cpufunc_asm_arm11x6.S
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@ -114,12 +114,7 @@ __FBSDID("$FreeBSD$");
#endif #endif
ENTRY(arm11x6_setttb) ENTRY(arm11x6_setttb)
#ifdef PMAP_CACHE_VIVT
Flush_D_cache(r1)
Invalidate_I_cache(r1, r2)
#else
mov r1, #0 mov r1, #0
#endif
mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLBs */ mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLBs */
mcr p15, 0, r1, c7, c10, 4 /* drain write buffer */ mcr p15, 0, r1, c7, c10, 4 /* drain write buffer */

4
sys/arm/arm/cpufunc_asm_armv6.S
View File

@ -49,10 +49,6 @@
* addresses that are about to change. * addresses that are about to change.
*/ */
ENTRY(armv6_setttb) ENTRY(armv6_setttb)
#ifdef PMAP_CACHE_VIVT
mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate D cache */
#endif
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ mcr p15, 0, r0, c2, c0, 0 /* load new TTB */