urtwn: add bits for R92C_HWSEQ_CTRL and R92C_TXPAUSE registers
Reviewed by: kevlo Approved by: adrian (mentor) Differential Revision: https://reviews.freebsd.org/D4770
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@ -2277,7 +2277,7 @@ urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
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case IEEE80211_S_SCAN:
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/* Pause AC Tx queues. */
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urtwn_write_1(sc, R92C_TXPAUSE,
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urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f);
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urtwn_read_1(sc, R92C_TXPAUSE) | R92C_TX_QUEUE_AC);
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break;
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case IEEE80211_S_AUTH:
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urtwn_set_chan(sc, ic->ic_curchan, NULL);
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@ -4425,7 +4425,7 @@ urtwn_lc_calib(struct urtwn_softc *sc)
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}
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} else {
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/* Block all Tx queues. */
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urtwn_write_1(sc, R92C_TXPAUSE, 0xff);
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urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
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}
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/* Start calibration. */
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urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
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@ -4640,7 +4640,7 @@ urtwn_init(struct urtwn_softc *sc)
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ieee80211_runtask(ic, &sc->cmdq_task);
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/* Enable hardware sequence numbering. */
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urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff);
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urtwn_write_1(sc, R92C_HWSEQ_CTRL, R92C_TX_QUEUE_ALL);
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/* Enable per-packet TX report. */
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if (sc->chip & URTWN_CHIP_88E) {
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@ -496,6 +496,24 @@
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#define R92C_EDCA_PARAM_TXOP_M 0xffff0000
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#define R92C_EDCA_PARAM_TXOP_S 16
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/* Bits for R92C_HWSEQ_CTRL / R92C_TXPAUSE. */
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#define R92C_TX_QUEUE_VO 0x01
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#define R92C_TX_QUEUE_VI 0x02
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#define R92C_TX_QUEUE_BE 0x04
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#define R92C_TX_QUEUE_BK 0x08
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#define R92C_TX_QUEUE_MGT 0x10
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#define R92C_TX_QUEUE_HIGH 0x20
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#define R92C_TX_QUEUE_BCN 0x40
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/* Shortcuts. */
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#define R92C_TX_QUEUE_AC \
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(R92C_TX_QUEUE_VO | R92C_TX_QUEUE_VI | \
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R92C_TX_QUEUE_BE | R92C_TX_QUEUE_BK)
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#define R92C_TX_QUEUE_ALL \
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(R92C_TX_QUEUE_AC | R92C_TX_QUEUE_MGT | \
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R92C_TX_QUEUE_HIGH | R92C_TX_QUEUE_BCN | 0x80) /* XXX */
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/* Bits for R92C_BCN_CTRL. */
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#define R92C_BCN_CTRL_EN_MBSSID 0x02
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#define R92C_BCN_CTRL_TXBCN_RPT 0x04
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