Add support for Intel's i820/i840/i845/i850/i860 chipset.
Submitted by: nork@cityfujisawa.ne.jp (Norikatsu Shigemura) PR: kern/31559, kern/31825 MFC after: 1 week
This commit is contained in:
Jun Kuriyama
parent
eacb362f8a
commit
6183dc49fb
@ -79,6 +79,21 @@ agp_intel_match(device_t dev)
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case 0x11308086:
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return ("Intel 82815 (i815 GMCH) host to PCI bridge");
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case 0x25008086:
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return ("Intel 82820 host to AGP bridge");
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case 0x1a218086:
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return ("Intel 82840 host to AGP bridge");
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case 0x1a308086:
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return ("Intel 82845 host to AGP bridge");
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case 0x25308086:
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return ("Intel 82850 host to AGP bridge");
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case 0x25318086:
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return ("Intel 82860 host to AGP bridge");
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};
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if (pci_get_vendor(dev) == 0x8086)
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@ -107,6 +122,7 @@ agp_intel_attach(device_t dev)
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{
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struct agp_intel_softc *sc = device_get_softc(dev);
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struct agp_gatt *gatt;
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u_int32_t type = pci_get_devid(dev);
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int error;
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error = agp_generic_attach(dev);
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@ -135,11 +151,52 @@ agp_intel_attach(device_t dev)
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pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4);
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/* Enable things, clear errors etc. */
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pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
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pci_write_config(dev, AGP_INTEL_NBXCFG,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 10)) | (1 << 9), 4);
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pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
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switch (type) {
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case 0x1a218086: /* i840 */
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case 0x25308086: /* i850 */
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case 0x25318086: /* i860 */
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pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
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pci_write_config(dev, AGP_INTEL_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
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| (1 << 9)), 2);
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break;
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case 0x25008086: /* i820 */
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pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
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pci_write_config(dev, AGP_INTEL_I820_RDCR,
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(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
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| (1 << 1)), 1);
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break;
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case 0x1a308086: /* i845 */
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pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
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pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
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| (1 << 1)), 1);
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break;
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default: /* Intel Generic (maybe) */
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pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
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pci_write_config(dev, AGP_INTEL_NBXCFG,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 10)) | (1 << 9), 4);
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}
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switch (type) {
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case 0x1a218086: /* i840 */
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pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
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break;
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case 0x25008086: /* i820 */
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case 0x1a308086: /* i845 */
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case 0x25308086: /* i850 */
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case 0x25318086: /* i860 */
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pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x001c, 2);
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break;
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default: /* Intel Generic (maybe) */
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pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
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}
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return 0;
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}
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@ -148,18 +205,48 @@ static int
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agp_intel_detach(device_t dev)
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{
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struct agp_intel_softc *sc = device_get_softc(dev);
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u_int32_t type = pci_get_devid(dev);
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int error;
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error = agp_generic_detach(dev);
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if (error)
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return error;
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printf("%s: set NBXCFG to %x\n", __FUNCTION__,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 9)));
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pci_write_config(dev, AGP_INTEL_NBXCFG,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 9)), 4);
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switch (type) {
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case 0x1a218086: /* i840 */
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case 0x25308086: /* i850 */
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case 0x25318086: /* i860 */
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printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
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(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
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& ~(1 << 9)));
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pci_write_config(dev, AGP_INTEL_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
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& ~(1 << 9)), 2);
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case 0x25008086: /* i820 */
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printf("%s: set RDCR to %x\n", __FUNCTION__, (unsigned)
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(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
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& ~(1 << 1)));
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pci_write_config(dev, AGP_INTEL_I820_RDCR,
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(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
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& ~(1 << 1)), 1);
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case 0x1a308086: /* i845 */
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printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
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(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
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& ~(1 << 1)));
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pci_write_config(dev, AGP_INTEL_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
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& ~(1 << 1)), 1);
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default: /* Intel Generic (maybe) */
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printf("%s: set NBXCFG to %x\n", __FUNCTION__,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 9)));
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pci_write_config(dev, AGP_INTEL_NBXCFG,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 9)), 4);
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}
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pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
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AGP_SET_APERTURE(dev, sc->initial_aperture);
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agp_free_gatt(sc->gatt);
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@ -56,6 +56,14 @@
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#define AGP_INTEL_APSIZE 0xb4
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#define AGP_INTEL_ATTBASE 0xb8
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/*
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* Config offsets for Intel i820/i840/i845/i850/i860 AGP chipsets.
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*/
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#define AGP_INTEL_MCHCFG 0x50
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#define AGP_INTEL_I820_RDCR 0x51
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#define AGP_INTEL_I845_MCHCFG 0x51
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#define AGP_INTEL_I8XX_ERRSTS 0xc8
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/*
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* Config offsets for VIA AGP chipsets.
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*/
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@ -79,6 +79,21 @@ agp_intel_match(device_t dev)
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case 0x11308086:
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return ("Intel 82815 (i815 GMCH) host to PCI bridge");
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case 0x25008086:
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return ("Intel 82820 host to AGP bridge");
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case 0x1a218086:
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return ("Intel 82840 host to AGP bridge");
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case 0x1a308086:
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return ("Intel 82845 host to AGP bridge");
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case 0x25308086:
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return ("Intel 82850 host to AGP bridge");
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case 0x25318086:
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return ("Intel 82860 host to AGP bridge");
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};
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if (pci_get_vendor(dev) == 0x8086)
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@ -107,6 +122,7 @@ agp_intel_attach(device_t dev)
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{
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struct agp_intel_softc *sc = device_get_softc(dev);
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struct agp_gatt *gatt;
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u_int32_t type = pci_get_devid(dev);
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int error;
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error = agp_generic_attach(dev);
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@ -135,11 +151,52 @@ agp_intel_attach(device_t dev)
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pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4);
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/* Enable things, clear errors etc. */
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pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
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pci_write_config(dev, AGP_INTEL_NBXCFG,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 10)) | (1 << 9), 4);
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pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
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switch (type) {
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case 0x1a218086: /* i840 */
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case 0x25308086: /* i850 */
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case 0x25318086: /* i860 */
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pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
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pci_write_config(dev, AGP_INTEL_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
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| (1 << 9)), 2);
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break;
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case 0x25008086: /* i820 */
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pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
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pci_write_config(dev, AGP_INTEL_I820_RDCR,
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(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
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| (1 << 1)), 1);
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break;
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case 0x1a308086: /* i845 */
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pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
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pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
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| (1 << 1)), 1);
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break;
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default: /* Intel Generic (maybe) */
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pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
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pci_write_config(dev, AGP_INTEL_NBXCFG,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 10)) | (1 << 9), 4);
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}
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switch (type) {
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case 0x1a218086: /* i840 */
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pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
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break;
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case 0x25008086: /* i820 */
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case 0x1a308086: /* i845 */
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case 0x25308086: /* i850 */
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case 0x25318086: /* i860 */
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pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x001c, 2);
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break;
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default: /* Intel Generic (maybe) */
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pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
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}
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return 0;
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}
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@ -148,18 +205,48 @@ static int
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agp_intel_detach(device_t dev)
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{
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struct agp_intel_softc *sc = device_get_softc(dev);
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u_int32_t type = pci_get_devid(dev);
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int error;
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error = agp_generic_detach(dev);
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if (error)
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return error;
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printf("%s: set NBXCFG to %x\n", __FUNCTION__,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 9)));
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pci_write_config(dev, AGP_INTEL_NBXCFG,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 9)), 4);
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switch (type) {
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case 0x1a218086: /* i840 */
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case 0x25308086: /* i850 */
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case 0x25318086: /* i860 */
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printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
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(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
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& ~(1 << 9)));
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pci_write_config(dev, AGP_INTEL_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
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& ~(1 << 9)), 2);
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case 0x25008086: /* i820 */
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printf("%s: set RDCR to %x\n", __FUNCTION__, (unsigned)
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(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
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& ~(1 << 1)));
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pci_write_config(dev, AGP_INTEL_I820_RDCR,
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(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
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& ~(1 << 1)), 1);
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case 0x1a308086: /* i845 */
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printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
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(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
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& ~(1 << 1)));
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pci_write_config(dev, AGP_INTEL_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
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& ~(1 << 1)), 1);
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default: /* Intel Generic (maybe) */
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printf("%s: set NBXCFG to %x\n", __FUNCTION__,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 9)));
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pci_write_config(dev, AGP_INTEL_NBXCFG,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 9)), 4);
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}
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pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
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AGP_SET_APERTURE(dev, sc->initial_aperture);
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agp_free_gatt(sc->gatt);
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@ -56,6 +56,14 @@
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#define AGP_INTEL_APSIZE 0xb4
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#define AGP_INTEL_ATTBASE 0xb8
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/*
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* Config offsets for Intel i820/i840/i845/i850/i860 AGP chipsets.
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*/
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#define AGP_INTEL_MCHCFG 0x50
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#define AGP_INTEL_I820_RDCR 0x51
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#define AGP_INTEL_I845_MCHCFG 0x51
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#define AGP_INTEL_I8XX_ERRSTS 0xc8
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/*
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* Config offsets for VIA AGP chipsets.
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*/
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