Regen cpuid assembly files for aarch64 and arm.
This commit is contained in:
Jung-uk Kim
parent
ea19bcde21
commit
61fab32360
@ -19,8 +19,11 @@
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PERLPATH= -I${LCRYPTO_SRC}/crypto/perlasm
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# cpuid
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SRCS= arm64cpuid.pl
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# aes
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SRCS= aesv8-armx.pl vpaes-armv8.pl
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SRCS+= aesv8-armx.pl vpaes-armv8.pl
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# bn
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SRCS+= armv8-mont.pl
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@ -157,8 +160,11 @@ ${s}.S: ${s}.s
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PERLPATH= -I${LCRYPTO_SRC}/crypto/perlasm
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# cpuid
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SRCS= armv4cpuid.pl
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# aes
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SRCS= aes-armv4.pl aesv8-armx.pl bsaes-armv7.pl
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SRCS+= aes-armv4.pl aesv8-armx.pl bsaes-armv7.pl
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# bn
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SRCS+= armv4-mont.pl armv4-gf2m.pl
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124
secure/lib/libcrypto/aarch64/arm64cpuid.S
Normal file
124
secure/lib/libcrypto/aarch64/arm64cpuid.S
Normal file
@ -0,0 +1,124 @@
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/* $FreeBSD$ */
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/* Do not modify. This file is auto-generated from arm64cpuid.pl. */
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#include "arm_arch.h"
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.text
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.arch armv8-a+crypto
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.align 5
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.globl _armv7_neon_probe
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.type _armv7_neon_probe,%function
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_armv7_neon_probe:
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orr v15.16b, v15.16b, v15.16b
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ret
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.size _armv7_neon_probe,.-_armv7_neon_probe
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.globl _armv7_tick
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.type _armv7_tick,%function
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_armv7_tick:
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#ifdef __APPLE__
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mrs x0, CNTPCT_EL0
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#else
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mrs x0, CNTVCT_EL0
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#endif
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ret
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.size _armv7_tick,.-_armv7_tick
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.globl _armv8_aes_probe
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.type _armv8_aes_probe,%function
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_armv8_aes_probe:
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aese v0.16b, v0.16b
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ret
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.size _armv8_aes_probe,.-_armv8_aes_probe
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.globl _armv8_sha1_probe
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.type _armv8_sha1_probe,%function
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_armv8_sha1_probe:
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sha1h s0, s0
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ret
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.size _armv8_sha1_probe,.-_armv8_sha1_probe
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.globl _armv8_sha256_probe
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.type _armv8_sha256_probe,%function
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_armv8_sha256_probe:
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sha256su0 v0.4s, v0.4s
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ret
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.size _armv8_sha256_probe,.-_armv8_sha256_probe
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.globl _armv8_pmull_probe
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.type _armv8_pmull_probe,%function
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_armv8_pmull_probe:
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pmull v0.1q, v0.1d, v0.1d
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ret
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.size _armv8_pmull_probe,.-_armv8_pmull_probe
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.globl _armv8_sha512_probe
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.type _armv8_sha512_probe,%function
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_armv8_sha512_probe:
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.long 0xcec08000 // sha512su0 v0.2d,v0.2d
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ret
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.size _armv8_sha512_probe,.-_armv8_sha512_probe
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.globl OPENSSL_cleanse
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.type OPENSSL_cleanse,%function
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.align 5
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OPENSSL_cleanse:
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cbz x1,.Lret // len==0?
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cmp x1,#15
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b.hi .Lot // len>15
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nop
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.Little:
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strb wzr,[x0],#1 // store byte-by-byte
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subs x1,x1,#1
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b.ne .Little
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.Lret: ret
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.align 4
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.Lot: tst x0,#7
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b.eq .Laligned // inp is aligned
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strb wzr,[x0],#1 // store byte-by-byte
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sub x1,x1,#1
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b .Lot
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.align 4
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.Laligned:
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str xzr,[x0],#8 // store word-by-word
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sub x1,x1,#8
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tst x1,#-8
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b.ne .Laligned // len>=8
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cbnz x1,.Little // len!=0?
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ret
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.size OPENSSL_cleanse,.-OPENSSL_cleanse
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.globl CRYPTO_memcmp
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.type CRYPTO_memcmp,%function
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.align 4
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CRYPTO_memcmp:
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eor w3,w3,w3
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cbz x2,.Lno_data // len==0?
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cmp x2,#16
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b.ne .Loop_cmp
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ldp x8,x9,[x0]
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ldp x10,x11,[x1]
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eor x8,x8,x10
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eor x9,x9,x11
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orr x8,x8,x9
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mov x0,#1
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cmp x8,#0
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csel x0,xzr,x0,eq
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ret
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.align 4
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.Loop_cmp:
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ldrb w4,[x0],#1
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ldrb w5,[x1],#1
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eor w4,w4,w5
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orr w3,w3,w4
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subs x2,x2,#1
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b.ne .Loop_cmp
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.Lno_data:
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neg w0,w3
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lsr w0,w0,#31
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ret
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.size CRYPTO_memcmp,.-CRYPTO_memcmp
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273
secure/lib/libcrypto/arm/armv4cpuid.S
Normal file
273
secure/lib/libcrypto/arm/armv4cpuid.S
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@ -0,0 +1,273 @@
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/* $FreeBSD$ */
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/* Do not modify. This file is auto-generated from armv4cpuid.pl. */
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#include "arm_arch.h"
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.text
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#if defined(__thumb2__) && !defined(__APPLE__)
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.syntax unified
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.thumb
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#else
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.code 32
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#undef __thumb2__
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#endif
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.align 5
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.globl OPENSSL_atomic_add
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.type OPENSSL_atomic_add,%function
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OPENSSL_atomic_add:
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#if __ARM_ARCH__>=6
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.Ladd: ldrex r2,[r0]
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add r3,r2,r1
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strex r2,r3,[r0]
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cmp r2,#0
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bne .Ladd
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mov r0,r3
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bx lr
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#else
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stmdb sp!,{r4,r5,r6,lr}
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ldr r2,.Lspinlock
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adr r3,.Lspinlock
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mov r4,r0
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mov r5,r1
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add r6,r3,r2 @ &spinlock
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b .+8
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.Lspin: bl sched_yield
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mov r0,#-1
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swp r0,r0,[r6]
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cmp r0,#0
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bne .Lspin
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ldr r2,[r4]
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add r2,r2,r5
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str r2,[r4]
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str r0,[r6] @ release spinlock
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ldmia sp!,{r4,r5,r6,lr}
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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#endif
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.size OPENSSL_atomic_add,.-OPENSSL_atomic_add
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.globl OPENSSL_cleanse
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.type OPENSSL_cleanse,%function
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OPENSSL_cleanse:
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eor ip,ip,ip
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cmp r1,#7
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#ifdef __thumb2__
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itt hs
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#endif
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subhs r1,r1,#4
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bhs .Lot
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cmp r1,#0
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beq .Lcleanse_done
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.Little:
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strb ip,[r0],#1
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subs r1,r1,#1
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bhi .Little
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b .Lcleanse_done
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.Lot: tst r0,#3
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beq .Laligned
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strb ip,[r0],#1
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sub r1,r1,#1
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b .Lot
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.Laligned:
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str ip,[r0],#4
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subs r1,r1,#4
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bhs .Laligned
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adds r1,r1,#4
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bne .Little
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.Lcleanse_done:
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#if __ARM_ARCH__>=5
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bx lr
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#else
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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#endif
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.size OPENSSL_cleanse,.-OPENSSL_cleanse
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.globl CRYPTO_memcmp
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.type CRYPTO_memcmp,%function
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.align 4
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CRYPTO_memcmp:
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eor ip,ip,ip
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cmp r2,#0
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beq .Lno_data
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stmdb sp!,{r4,r5}
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.Loop_cmp:
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ldrb r4,[r0],#1
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ldrb r5,[r1],#1
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eor r4,r4,r5
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orr ip,ip,r4
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subs r2,r2,#1
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bne .Loop_cmp
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ldmia sp!,{r4,r5}
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.Lno_data:
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rsb r0,ip,#0
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mov r0,r0,lsr#31
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#if __ARM_ARCH__>=5
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bx lr
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#else
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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#endif
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.size CRYPTO_memcmp,.-CRYPTO_memcmp
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#if __ARM_MAX_ARCH__>=7
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.arch armv7-a
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.fpu neon
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.align 5
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.globl _armv7_neon_probe
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.type _armv7_neon_probe,%function
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_armv7_neon_probe:
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vorr q0,q0,q0
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bx lr
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.size _armv7_neon_probe,.-_armv7_neon_probe
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.globl _armv7_tick
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.type _armv7_tick,%function
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_armv7_tick:
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#ifdef __APPLE__
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mrrc p15,0,r0,r1,c14 @ CNTPCT
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#else
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mrrc p15,1,r0,r1,c14 @ CNTVCT
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#endif
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bx lr
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.size _armv7_tick,.-_armv7_tick
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.globl _armv8_aes_probe
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.type _armv8_aes_probe,%function
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_armv8_aes_probe:
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#if defined(__thumb2__) && !defined(__APPLE__)
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.byte 0xb0,0xff,0x00,0x03 @ aese.8 q0,q0
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#else
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.byte 0x00,0x03,0xb0,0xf3 @ aese.8 q0,q0
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#endif
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bx lr
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.size _armv8_aes_probe,.-_armv8_aes_probe
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.globl _armv8_sha1_probe
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.type _armv8_sha1_probe,%function
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_armv8_sha1_probe:
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#if defined(__thumb2__) && !defined(__APPLE__)
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.byte 0x00,0xef,0x40,0x0c @ sha1c.32 q0,q0,q0
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#else
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.byte 0x40,0x0c,0x00,0xf2 @ sha1c.32 q0,q0,q0
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#endif
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bx lr
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.size _armv8_sha1_probe,.-_armv8_sha1_probe
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.globl _armv8_sha256_probe
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.type _armv8_sha256_probe,%function
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_armv8_sha256_probe:
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#if defined(__thumb2__) && !defined(__APPLE__)
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.byte 0x00,0xff,0x40,0x0c @ sha256h.32 q0,q0,q0
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#else
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.byte 0x40,0x0c,0x00,0xf3 @ sha256h.32 q0,q0,q0
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#endif
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bx lr
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.size _armv8_sha256_probe,.-_armv8_sha256_probe
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.globl _armv8_pmull_probe
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.type _armv8_pmull_probe,%function
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_armv8_pmull_probe:
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#if defined(__thumb2__) && !defined(__APPLE__)
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.byte 0xa0,0xef,0x00,0x0e @ vmull.p64 q0,d0,d0
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#else
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.byte 0x00,0x0e,0xa0,0xf2 @ vmull.p64 q0,d0,d0
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#endif
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bx lr
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.size _armv8_pmull_probe,.-_armv8_pmull_probe
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#endif
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.globl OPENSSL_wipe_cpu
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.type OPENSSL_wipe_cpu,%function
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OPENSSL_wipe_cpu:
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#if __ARM_MAX_ARCH__>=7
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ldr r0,.LOPENSSL_armcap
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adr r1,.LOPENSSL_armcap
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ldr r0,[r1,r0]
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#ifdef __APPLE__
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ldr r0,[r0]
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#endif
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#endif
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eor r2,r2,r2
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eor r3,r3,r3
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eor ip,ip,ip
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#if __ARM_MAX_ARCH__>=7
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tst r0,#1
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beq .Lwipe_done
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veor q0, q0, q0
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veor q1, q1, q1
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veor q2, q2, q2
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veor q3, q3, q3
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veor q8, q8, q8
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veor q9, q9, q9
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veor q10, q10, q10
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veor q11, q11, q11
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veor q12, q12, q12
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veor q13, q13, q13
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veor q14, q14, q14
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veor q15, q15, q15
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.Lwipe_done:
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#endif
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mov r0,sp
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#if __ARM_ARCH__>=5
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bx lr
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#else
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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#endif
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.size OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu
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.globl OPENSSL_instrument_bus
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.type OPENSSL_instrument_bus,%function
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OPENSSL_instrument_bus:
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eor r0,r0,r0
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#if __ARM_ARCH__>=5
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bx lr
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#else
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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#endif
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.size OPENSSL_instrument_bus,.-OPENSSL_instrument_bus
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.globl OPENSSL_instrument_bus2
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.type OPENSSL_instrument_bus2,%function
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OPENSSL_instrument_bus2:
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eor r0,r0,r0
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#if __ARM_ARCH__>=5
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bx lr
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#else
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tst lr,#1
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moveq pc,lr
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.word 0xe12fff1e @ bx lr
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#endif
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.size OPENSSL_instrument_bus2,.-OPENSSL_instrument_bus2
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.align 5
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#if __ARM_MAX_ARCH__>=7
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.LOPENSSL_armcap:
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.word OPENSSL_armcap_P-.
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#endif
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#if __ARM_ARCH__>=6
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.align 5
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#else
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.Lspinlock:
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.word atomic_add_spinlock-.Lspinlock
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.align 5
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.data
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.align 2
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atomic_add_spinlock:
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.word 0
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#endif
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.comm OPENSSL_armcap_P,4,4
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.hidden OPENSSL_armcap_P
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