Updated ixgbe driver - version 1.6.2
-This version has header split, and as a result a number of aspects of the code have been improved/simplified. - Interrupt handling refined for performance - Many small bugs fixed along the way MFC after: ASAP - in time for 7.1
This commit is contained in:
jfv
parent
8c32a34157
commit
62188214bd
File diff suppressed because it is too large
Load Diff
@ -32,6 +32,7 @@
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******************************************************************************/
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/*$FreeBSD$*/
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#ifndef _IXGBE_H_
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#define _IXGBE_H_
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@ -63,7 +64,6 @@
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#include <netinet/ip.h>
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#include <netinet/ip6.h>
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#include <netinet/tcp.h>
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#include <netinet/tcp_lro.h>
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#include <netinet/udp.h>
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#include <machine/in_cksum.h>
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@ -84,6 +84,7 @@
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#include <sys/pcpu.h>
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#include "ixgbe_api.h"
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#include "tcp_lro.h"
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/* Tunables */
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@ -121,7 +122,7 @@
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* This parameter controls the maximum no of times the driver will loop in
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* the isr. Minimum Value = 1
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*/
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#define MAX_INTR 10
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#define MAX_LOOP 10
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/*
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* This parameter controls the duration of transmit watchdog timer.
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@ -159,10 +160,11 @@
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#define MAX_NUM_MULTICAST_ADDRESSES 128
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#define IXGBE_MAX_SCATTER 100
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#define IXGBE_MSIX_BAR 3
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#define MSIX_82598_BAR 3
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#define MSIX_82599_BAR 4
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#define IXGBE_TSO_SIZE 65535
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#define IXGBE_TX_BUFFER_SIZE ((u32) 1514)
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#define IXGBE_RX_HDR_SIZE ((u32) 256)
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#define IXGBE_RX_HDR 128
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#define CSUM_OFFLOAD 7 /* Bits in csum flags */
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/* The number of MSIX messages the 82598 supports */
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@ -179,24 +181,28 @@
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/*
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* Interrupt Moderation parameters
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* for now we hardcode, later
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* it would be nice to do dynamic
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*/
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#define MAX_IRQ_SEC 8000
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#define DEFAULT_ITR 1000000000/(MAX_IRQ_SEC * 256)
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#define LINK_ITR 1000000000/(1950 * 256)
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#define IXGBE_LOW_LATENCY 128
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#define IXGBE_AVE_LATENCY 400
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#define IXGBE_BULK_LATENCY 1200
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#define IXGBE_LINK_ITR 2000
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/* Header split args for get_bug */
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#define IXGBE_CLEAN_HDR 1
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#define IXGBE_CLEAN_PKT 2
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#define IXGBE_CLEAN_ALL 3
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/* Used for auto RX queue configuration */
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extern int mp_ncpus;
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/*
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* ******************************************************************************
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*****************************************************************************
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* vendor_info_array
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*
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* This array contains the list of Subvendor/Subdevice IDs on which the driver
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* should load.
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*
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*****************************************************************************
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*****************************************************************************
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*/
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typedef struct _ixgbe_vendor_info_t {
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unsigned int vendor_id;
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@ -204,7 +210,7 @@ typedef struct _ixgbe_vendor_info_t {
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unsigned int subvendor_id;
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unsigned int subdevice_id;
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unsigned int index;
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} ixgbe_vendor_info_t;
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} ixgbe_vendor_info_t;
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struct ixgbe_tx_buf {
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@ -214,9 +220,8 @@ struct ixgbe_tx_buf {
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struct ixgbe_rx_buf {
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struct mbuf *m_head;
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boolean_t bigbuf;
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/* one small and one large map */
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bus_dmamap_t map[2];
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struct mbuf *m_pack;
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bus_dmamap_t map;
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};
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/*
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@ -253,11 +258,12 @@ struct tx_ring {
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volatile u16 tx_avail;
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u32 txd_cmd;
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bus_dma_tag_t txtag;
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char mtx_name[16];
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/* Soft Stats */
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u32 no_tx_desc_avail;
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u32 no_tx_desc_late;
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u64 tx_irq;
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u64 tx_packets;
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u64 total_packets;
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};
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@ -279,14 +285,20 @@ struct rx_ring {
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unsigned int last_cleaned;
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unsigned int next_to_check;
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struct ixgbe_rx_buf *rx_buffers;
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bus_dma_tag_t rxtag[2];
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bus_dmamap_t spare_map[2];
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bus_dma_tag_t rxtag;
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bus_dmamap_t spare_map;
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struct mbuf *fmp;
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struct mbuf *lmp;
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char mtx_name[16];
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u32 bytes; /* Used for AIM calc */
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u32 eitr_setting;
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/* Soft stats */
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u64 rx_irq;
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u64 packet_count;
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u64 byte_count;
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u64 rx_split_packets;
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u64 rx_packets;
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u64 rx_bytes;
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};
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/* Our adapter structure */
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@ -294,7 +306,6 @@ struct adapter {
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struct ifnet *ifp;
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struct ixgbe_hw hw;
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/* FreeBSD operating-system-specific structures */
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struct ixgbe_osdep osdep;
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struct device *dev;
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@ -309,7 +320,6 @@ struct adapter {
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void *tag[IXGBE_MSGS];
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struct resource *res[IXGBE_MSGS];
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int rid[IXGBE_MSGS];
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u32 eims_mask;
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struct ifmedia media;
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struct callout timer;
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@ -318,21 +328,23 @@ struct adapter {
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struct mtx core_mtx;
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/* Legacy Fast Intr handling */
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struct task link_task;
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/* Info about the board itself */
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u32 part_num;
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u32 optics;
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bool link_active;
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u16 max_frame_size;
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u32 link_speed;
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u32 linkvec;
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u32 tx_int_delay;
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u32 tx_abs_int_delay;
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u32 rx_int_delay;
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u32 rx_abs_int_delay;
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/* Indicates the cluster size to use */
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bool bigbufs;
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/* Mbuf cluster size */
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u32 rx_mbuf_sz;
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/* Check for missing optics */
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bool sfp_probe;
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/*
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* Transmit rings:
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@ -349,20 +361,18 @@ struct adapter {
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struct rx_ring *rx_rings;
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int num_rx_desc;
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int num_rx_queues;
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u32 rx_mask;
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u32 rx_process_limit;
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eventhandler_tag vlan_attach;
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eventhandler_tag vlan_detach;
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/* Misc stats maintained by the driver */
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unsigned long dropped_pkts;
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unsigned long mbuf_alloc_failed;
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unsigned long mbuf_cluster_failed;
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unsigned long mbuf_defrag_failed;
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unsigned long mbuf_header_failed;
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unsigned long mbuf_packet_failed;
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unsigned long no_tx_map_avail;
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unsigned long no_tx_dma_setup;
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unsigned long watchdog_events;
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unsigned long tso_tx;
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unsigned long linkvec;
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unsigned long link_irq;
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struct ixgbe_hw_stats stats;
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File diff suppressed because it is too large
Load Diff
@ -47,7 +47,7 @@ extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
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* memset to 0 prior to calling this function. The following fields in
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* hw structure should be filled in prior to calling this function:
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* hw_addr, back, device_id, vendor_id, subsystem_device_id,
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* subsystem_vendor_id, and revision_id
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* subsystem_vendor_id, and revision_id
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**/
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s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
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{
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@ -85,13 +85,16 @@ s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
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if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) {
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switch (hw->device_id) {
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case IXGBE_DEV_ID_82598:
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case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
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case IXGBE_DEV_ID_82598AF_DUAL_PORT:
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case IXGBE_DEV_ID_82598AT:
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case IXGBE_DEV_ID_82598AT_DUAL_PORT:
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case IXGBE_DEV_ID_82598EB_CX4:
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case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
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case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
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case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
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case IXGBE_DEV_ID_82598EB_XF_LR:
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case IXGBE_DEV_ID_82598EB_SFP_LOM:
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hw->mac.type = ixgbe_mac_82598EB;
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break;
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default:
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@ -279,9 +282,8 @@ s32 ixgbe_reset_phy(struct ixgbe_hw *hw)
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s32 status = IXGBE_SUCCESS;
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if (hw->phy.type == ixgbe_phy_unknown) {
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if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) {
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status = IXGBE_ERR_PHY;
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}
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if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS)
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status = IXGBE_ERR_PHY;
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}
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if (status == IXGBE_SUCCESS) {
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@ -766,11 +768,38 @@ s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)
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* ixgbe_init_uta_tables - Initializes Unicast Table Arrays.
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* @hw: pointer to hardware structure
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*
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* Initializes the Unicast Table Arrays to zero on device load. This
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* is part of the Rx init addr execution path.
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* Initializes the Unicast Table Arrays to zero on device load. This
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* is part of the Rx init addr execution path.
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**/
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s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw)
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{
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return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw),
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IXGBE_NOT_IMPLEMENTED);
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}
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/**
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* ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
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* @hw: pointer to hardware structure
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* @byte_offset: EEPROM byte offset to read
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* @eeprom_data: value read
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*
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* Performs byte read operation to SFP module's EEPROM over I2C interface.
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**/
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s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)
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{
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return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom,
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(hw, byte_offset, eeprom_data),
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IXGBE_NOT_IMPLEMENTED);
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}
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/**
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* ixgbe_get_supported_physical_layer - Returns physical layer type
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* @hw: pointer to hardware structure
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*
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* Determines physical layer capabilities of the current configuration.
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**/
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u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)
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{
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return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,
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(hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);
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}
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@ -110,5 +110,7 @@ s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw,
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s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);
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s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);
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s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw);
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s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data);
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u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw);
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#endif /* _IXGBE_API_H_ */
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@ -85,11 +85,11 @@ s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
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mac->ops.start_hw = &ixgbe_start_hw_generic;
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mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
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mac->ops.get_media_type = NULL;
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mac->ops.get_supported_physical_layer = NULL;
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mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
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mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
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mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
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mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_generic;
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mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_generic;
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mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
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/* LEDs */
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mac->ops.led_on = &ixgbe_led_on_generic;
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@ -111,8 +111,6 @@ s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
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mac->ops.set_vfta = NULL;
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mac->ops.init_uta_tables = NULL;
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/* Flow Control */
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mac->ops.setup_fc = NULL;
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/* Link */
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mac->ops.get_link_capabilities = NULL;
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@ -215,17 +213,16 @@ s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
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IXGBE_READ_REG(hw, IXGBE_MRFC);
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IXGBE_READ_REG(hw, IXGBE_RLEC);
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IXGBE_READ_REG(hw, IXGBE_LXONTXC);
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IXGBE_READ_REG(hw, IXGBE_LXONRXC);
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IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
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IXGBE_READ_REG(hw, IXGBE_LXONRXC);
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IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
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for (i = 0; i < 8; i++) {
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IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
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IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
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IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
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IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
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IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
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}
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IXGBE_READ_REG(hw, IXGBE_PRC64);
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IXGBE_READ_REG(hw, IXGBE_PRC127);
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IXGBE_READ_REG(hw, IXGBE_PRC255);
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@ -272,7 +269,7 @@ s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
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}
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/**
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* ixgbe_read_pba_num - Reads part number from EEPROM
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* ixgbe_read_pba_num_generic - Reads part number from EEPROM
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* @hw: pointer to hardware structure
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* @pba_num: stores the part number from the EEPROM
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*
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@ -337,6 +334,7 @@ s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
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**/
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s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
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{
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struct ixgbe_mac_info *mac = &hw->mac;
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u16 link_status;
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hw->bus.type = ixgbe_bus_type_pci_express;
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@ -374,9 +372,32 @@ s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
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break;
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}
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mac->ops.set_lan_id(hw);
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return IXGBE_SUCCESS;
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}
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/**
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* ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
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* @hw: pointer to the HW structure
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*
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* Determines the LAN function id by reading memory-mapped registers
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* and swaps the port value if requested.
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**/
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void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
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{
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struct ixgbe_bus_info *bus = &hw->bus;
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u32 reg;
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reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
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bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
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/* check for a port swap */
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reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
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if (reg & IXGBE_FACTPS_LFS)
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bus->func ^= 0x1;
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}
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/**
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* ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
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* @hw: pointer to hardware structure
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@ -425,9 +446,8 @@ s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
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* Prevent the PCI-E bus from from hanging by disabling PCI-E master
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* access and verify no pending requests
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*/
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if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) {
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if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS)
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DEBUGOUT("PCI-E Master disable polling has failed.\n");
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}
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return IXGBE_SUCCESS;
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}
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@ -500,9 +520,9 @@ s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
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* change if a future EEPROM is not SPI.
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*/
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eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
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IXGBE_EEC_SIZE_SHIFT);
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IXGBE_EEC_SIZE_SHIFT);
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eeprom->word_size = 1 << (eeprom_size +
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IXGBE_EEPROM_WORD_SIZE_SHIFT);
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IXGBE_EEPROM_WORD_SIZE_SHIFT);
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}
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if (eec & IXGBE_EEC_ADDR_SIZE)
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@ -510,8 +530,8 @@ s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
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else
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eeprom->address_bits = 8;
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DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
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"%d\n", eeprom->type, eeprom->word_size,
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eeprom->address_bits);
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"%d\n", eeprom->type, eeprom->word_size,
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eeprom->address_bits);
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}
|
||||
|
||||
return IXGBE_SUCCESS;
|
||||
@ -1156,7 +1176,7 @@ s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
|
||||
if (status == IXGBE_SUCCESS) {
|
||||
checksum = ixgbe_calc_eeprom_checksum(hw);
|
||||
status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
|
||||
checksum);
|
||||
checksum);
|
||||
} else {
|
||||
DEBUGOUT("EEPROM read failed\n");
|
||||
}
|
||||
@ -1453,7 +1473,7 @@ s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
|
||||
if (hw->addr_ctrl.overflow_promisc) {
|
||||
/* enable promisc if not already in overflow or set by user */
|
||||
if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
|
||||
DEBUGOUT( " Entering address overflow promisc mode\n");
|
||||
DEBUGOUT(" Entering address overflow promisc mode\n");
|
||||
fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
|
||||
fctrl |= IXGBE_FCTRL_UPE;
|
||||
IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
|
||||
@ -1684,6 +1704,148 @@ s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
|
||||
return IXGBE_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* ixgbe_fc_autoneg - Configure flow control
|
||||
* @hw: pointer to hardware structure
|
||||
*
|
||||
* Negotiates flow control capabilities with link partner using autoneg and
|
||||
* applies the results.
|
||||
**/
|
||||
s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
|
||||
{
|
||||
s32 ret_val = IXGBE_SUCCESS;
|
||||
u32 i, reg, pcs_anadv_reg, pcs_lpab_reg;
|
||||
|
||||
DEBUGFUNC("ixgbe_fc_autoneg");
|
||||
|
||||
reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
|
||||
|
||||
/*
|
||||
* The possible values of fc.current_mode are:
|
||||
* 0: Flow control is completely disabled
|
||||
* 1: Rx flow control is enabled (we can receive pause frames,
|
||||
* but not send pause frames).
|
||||
* 2: Tx flow control is enabled (we can send pause frames but
|
||||
* we do not support receiving pause frames).
|
||||
* 3: Both Rx and Tx flow control (symmetric) are enabled.
|
||||
* other: Invalid.
|
||||
*/
|
||||
switch (hw->fc.current_mode) {
|
||||
case ixgbe_fc_none:
|
||||
/* Flow control completely disabled by software override. */
|
||||
reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
|
||||
break;
|
||||
case ixgbe_fc_rx_pause:
|
||||
/*
|
||||
* Rx Flow control is enabled and Tx Flow control is
|
||||
* disabled by software override. Since there really
|
||||
* isn't a way to advertise that we are capable of RX
|
||||
* Pause ONLY, we will advertise that we support both
|
||||
* symmetric and asymmetric Rx PAUSE. Later, we will
|
||||
* disable the adapter's ability to send PAUSE frames.
|
||||
*/
|
||||
reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
|
||||
break;
|
||||
case ixgbe_fc_tx_pause:
|
||||
/*
|
||||
* Tx Flow control is enabled, and Rx Flow control is
|
||||
* disabled by software override.
|
||||
*/
|
||||
reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
|
||||
reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
|
||||
break;
|
||||
case ixgbe_fc_full:
|
||||
/* Flow control (both Rx and Tx) is enabled by SW override. */
|
||||
reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
|
||||
break;
|
||||
default:
|
||||
DEBUGOUT("Flow control param set incorrectly\n");
|
||||
ret_val = -IXGBE_ERR_CONFIG;
|
||||
goto out;
|
||||
break;
|
||||
}
|
||||
|
||||
IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
|
||||
reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
|
||||
|
||||
/* Set PCS register for autoneg */
|
||||
/* Enable and restart autoneg */
|
||||
reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART;
|
||||
|
||||
/* Disable AN timeout */
|
||||
if (hw->fc.strict_ieee)
|
||||
reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
|
||||
|
||||
DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
|
||||
IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
|
||||
|
||||
/* See if autonegotiation has succeeded */
|
||||
hw->mac.autoneg_succeeded = 0;
|
||||
for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
|
||||
msec_delay(10);
|
||||
reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
|
||||
if ((reg & (IXGBE_PCS1GLSTA_LINK_OK |
|
||||
IXGBE_PCS1GLSTA_AN_COMPLETE)) ==
|
||||
(IXGBE_PCS1GLSTA_LINK_OK |
|
||||
IXGBE_PCS1GLSTA_AN_COMPLETE)) {
|
||||
if (!(reg & IXGBE_PCS1GLSTA_AN_TIMED_OUT))
|
||||
hw->mac.autoneg_succeeded = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!hw->mac.autoneg_succeeded) {
|
||||
/* Autoneg failed to achieve a link, so we turn fc off */
|
||||
hw->fc.current_mode = ixgbe_fc_none;
|
||||
DEBUGOUT("Flow Control = NONE.\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read the AN advertisement and LP ability registers and resolve
|
||||
* local flow control settings accordingly
|
||||
*/
|
||||
pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
|
||||
pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
|
||||
if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
|
||||
(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
|
||||
/*
|
||||
* Now we need to check if the user selected Rx ONLY
|
||||
* of pause frames. In this case, we had to advertise
|
||||
* FULL flow control because we could not advertise RX
|
||||
* ONLY. Hence, we must now check to see if we need to
|
||||
* turn OFF the TRANSMISSION of PAUSE frames.
|
||||
*/
|
||||
if (hw->fc.requested_mode == ixgbe_fc_full) {
|
||||
hw->fc.current_mode = ixgbe_fc_full;
|
||||
DEBUGOUT("Flow Control = FULL.\n");
|
||||
} else {
|
||||
hw->fc.current_mode = ixgbe_fc_rx_pause;
|
||||
DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
|
||||
}
|
||||
} else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
|
||||
(pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
|
||||
(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
|
||||
(pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
|
||||
hw->fc.current_mode = ixgbe_fc_tx_pause;
|
||||
DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
|
||||
} else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
|
||||
(pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
|
||||
!(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
|
||||
(pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
|
||||
hw->fc.current_mode = ixgbe_fc_rx_pause;
|
||||
DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
|
||||
} else {
|
||||
hw->fc.current_mode = ixgbe_fc_none;
|
||||
DEBUGOUT("Flow Control = NONE.\n");
|
||||
}
|
||||
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* ixgbe_disable_pcie_master - Disable PCI-express master access
|
||||
* @hw: pointer to hardware structure
|
||||
@ -1792,44 +1954,3 @@ void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
|
||||
ixgbe_release_eeprom_semaphore(hw);
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_read_analog_reg8_generic - Reads 8 bit Atlas analog register
|
||||
* @hw: pointer to hardware structure
|
||||
* @reg: analog register to read
|
||||
* @val: read value
|
||||
*
|
||||
* Performs read operation to Atlas analog register specified.
|
||||
**/
|
||||
s32 ixgbe_read_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 *val)
|
||||
{
|
||||
u32 atlas_ctl;
|
||||
|
||||
IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
|
||||
IXGBE_WRITE_FLUSH(hw);
|
||||
usec_delay(10);
|
||||
atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
|
||||
*val = (u8)atlas_ctl;
|
||||
|
||||
return IXGBE_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_write_analog_reg8_generic - Writes 8 bit Atlas analog register
|
||||
* @hw: pointer to hardware structure
|
||||
* @reg: atlas register to write
|
||||
* @val: value to write
|
||||
*
|
||||
* Performs write operation to Atlas analog register specified.
|
||||
**/
|
||||
s32 ixgbe_write_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 val)
|
||||
{
|
||||
u32 atlas_ctl;
|
||||
|
||||
atlas_ctl = (reg << 8) | val;
|
||||
IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
|
||||
IXGBE_WRITE_FLUSH(hw);
|
||||
usec_delay(10);
|
||||
|
||||
return IXGBE_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
@ -44,6 +44,7 @@ s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num);
|
||||
s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
|
||||
s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
|
||||
void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);
|
||||
|
||||
s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);
|
||||
@ -70,6 +71,10 @@ s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
|
||||
s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
|
||||
|
||||
s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw, s32 packetbuf_num);
|
||||
s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packtetbuf_num);
|
||||
s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw);
|
||||
|
||||
s32 ixgbe_validate_mac_addr(u8 *mac_addr);
|
||||
s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);
|
||||
void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask);
|
||||
|
||||
@ -78,16 +78,21 @@
|
||||
#endif
|
||||
|
||||
#define FALSE 0
|
||||
#define false 0 /* shared code requires this */
|
||||
#define TRUE 1
|
||||
#define true 1
|
||||
#define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
|
||||
#define PCI_COMMAND_REGISTER PCIR_COMMAND
|
||||
|
||||
typedef uint8_t u8;
|
||||
typedef uint16_t u16;
|
||||
typedef uint32_t u32;
|
||||
typedef int32_t s32;
|
||||
typedef uint64_t u64;
|
||||
typedef boolean_t bool;
|
||||
#define IXGBE_HTONL htonl
|
||||
|
||||
typedef uint8_t u8;
|
||||
typedef int8_t s8;
|
||||
typedef uint16_t u16;
|
||||
typedef uint32_t u32;
|
||||
typedef int32_t s32;
|
||||
typedef uint64_t u64;
|
||||
typedef boolean_t bool;
|
||||
|
||||
#define le16_to_cpu
|
||||
|
||||
|
||||
@ -55,6 +55,8 @@ s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
|
||||
phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
|
||||
phy->ops.check_link = NULL;
|
||||
phy->ops.get_firmware_version = NULL;
|
||||
phy->ops.identify_sfp = &ixgbe_identify_sfp_module_generic;
|
||||
phy->sfp_type = ixgbe_sfp_type_unknown;
|
||||
|
||||
return IXGBE_SUCCESS;
|
||||
}
|
||||
@ -131,7 +133,6 @@ s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
|
||||
hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
|
||||
hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
@ -151,6 +152,9 @@ enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
|
||||
case QT2022_PHY_ID:
|
||||
phy_type = ixgbe_phy_qt;
|
||||
break;
|
||||
case ATH_PHY_ID:
|
||||
phy_type = ixgbe_phy_nl;
|
||||
break;
|
||||
default:
|
||||
phy_type = ixgbe_phy_unknown;
|
||||
break;
|
||||
@ -217,9 +221,8 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
|
||||
|
||||
command = IXGBE_READ_REG(hw, IXGBE_MSCA);
|
||||
|
||||
if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) {
|
||||
if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
|
||||
@ -445,12 +448,11 @@ s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
|
||||
*/
|
||||
hw->phy.autoneg_advertised = 0;
|
||||
|
||||
if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
|
||||
if (speed & IXGBE_LINK_SPEED_10GB_FULL)
|
||||
hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
|
||||
}
|
||||
if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
|
||||
|
||||
if (speed & IXGBE_LINK_SPEED_1GB_FULL)
|
||||
hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
|
||||
}
|
||||
|
||||
/* Setup link based on the new speed settings */
|
||||
hw->phy.ops.setup_link(hw);
|
||||
@ -523,3 +525,262 @@ s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_reset_phy_nl - Performs a PHY reset
|
||||
* @hw: pointer to hardware structure
|
||||
**/
|
||||
s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
|
||||
{
|
||||
u16 phy_offset, control, eword, edata, block_crc;
|
||||
bool end_data = FALSE;
|
||||
u16 list_offset, data_offset;
|
||||
u16 phy_data = 0;
|
||||
s32 ret_val = IXGBE_SUCCESS;
|
||||
u32 i;
|
||||
|
||||
hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
|
||||
IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
|
||||
|
||||
/* reset the PHY and poll for completion */
|
||||
hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
|
||||
IXGBE_MDIO_PHY_XS_DEV_TYPE,
|
||||
(phy_data | IXGBE_MDIO_PHY_XS_RESET));
|
||||
|
||||
for (i = 0; i < 100; i++) {
|
||||
hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
|
||||
IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
|
||||
if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
|
||||
break;
|
||||
msec_delay(10);
|
||||
}
|
||||
|
||||
if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
|
||||
DEBUGOUT("PHY reset did not complete.\n");
|
||||
ret_val = IXGBE_ERR_PHY;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Get init offsets */
|
||||
ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
|
||||
&data_offset);
|
||||
if (ret_val != IXGBE_SUCCESS)
|
||||
goto out;
|
||||
|
||||
ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
|
||||
data_offset++;
|
||||
while (!end_data) {
|
||||
/*
|
||||
* Read control word from PHY init contents offset
|
||||
*/
|
||||
ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
|
||||
control = (eword & IXGBE_CONTROL_MASK_NL) >>
|
||||
IXGBE_CONTROL_SHIFT_NL;
|
||||
edata = eword & IXGBE_DATA_MASK_NL;
|
||||
switch (control) {
|
||||
case IXGBE_DELAY_NL:
|
||||
data_offset++;
|
||||
DEBUGOUT1("DELAY: %d MS\n", edata);
|
||||
msec_delay(edata);
|
||||
break;
|
||||
case IXGBE_DATA_NL:
|
||||
DEBUGOUT("DATA: \n");
|
||||
data_offset++;
|
||||
hw->eeprom.ops.read(hw, data_offset++,
|
||||
&phy_offset);
|
||||
for (i = 0; i < edata; i++) {
|
||||
hw->eeprom.ops.read(hw, data_offset, &eword);
|
||||
hw->phy.ops.write_reg(hw, phy_offset,
|
||||
IXGBE_TWINAX_DEV, eword);
|
||||
DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
|
||||
phy_offset);
|
||||
data_offset++;
|
||||
phy_offset++;
|
||||
}
|
||||
break;
|
||||
case IXGBE_CONTROL_NL:
|
||||
data_offset++;
|
||||
DEBUGOUT("CONTROL: \n");
|
||||
if (edata == IXGBE_CONTROL_EOL_NL) {
|
||||
DEBUGOUT("EOL\n");
|
||||
end_data = TRUE;
|
||||
} else if (edata == IXGBE_CONTROL_SOL_NL) {
|
||||
DEBUGOUT("SOL\n");
|
||||
} else {
|
||||
DEBUGOUT("Bad control value\n");
|
||||
ret_val = IXGBE_ERR_PHY;
|
||||
goto out;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
DEBUGOUT("Bad control type\n");
|
||||
ret_val = IXGBE_ERR_PHY;
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_identify_sfp_module_generic - Identifies SFP modules
|
||||
* @hw: pointer to hardware structure
|
||||
*
|
||||
* Searches for and identifies the SFP module and assigns appropriate PHY type.
|
||||
**/
|
||||
s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
|
||||
{
|
||||
s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
|
||||
u32 vendor_oui = 0;
|
||||
u8 identifier = 0;
|
||||
u8 comp_codes_1g = 0;
|
||||
u8 comp_codes_10g = 0;
|
||||
u8 oui_bytes[4] = {0, 0, 0, 0};
|
||||
u8 transmission_media = 0;
|
||||
|
||||
status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
|
||||
&identifier);
|
||||
|
||||
if (status == IXGBE_ERR_SFP_NOT_PRESENT) {
|
||||
hw->phy.sfp_type = ixgbe_sfp_type_not_present;
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (identifier == IXGBE_SFF_IDENTIFIER_SFP) {
|
||||
hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES,
|
||||
&comp_codes_1g);
|
||||
hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES,
|
||||
&comp_codes_10g);
|
||||
hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_TRANSMISSION_MEDIA,
|
||||
&transmission_media);
|
||||
|
||||
/* ID Module
|
||||
* =========
|
||||
* 0 SFP_DA_CU
|
||||
* 1 SFP_SR
|
||||
* 2 SFP_LR
|
||||
*/
|
||||
if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE)
|
||||
hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
|
||||
else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
|
||||
hw->phy.sfp_type = ixgbe_sfp_type_sr;
|
||||
else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
|
||||
hw->phy.sfp_type = ixgbe_sfp_type_lr;
|
||||
else
|
||||
hw->phy.sfp_type = ixgbe_sfp_type_unknown;
|
||||
|
||||
/* Determine if the SFP+ PHY is dual speed or not. */
|
||||
if ((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
|
||||
(comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE))
|
||||
hw->phy.multispeed_fiber = TRUE;
|
||||
/* Determine PHY vendor */
|
||||
if (hw->phy.type == ixgbe_phy_unknown) {
|
||||
hw->phy.id = identifier;
|
||||
hw->phy.ops.read_i2c_eeprom(hw,
|
||||
IXGBE_SFF_VENDOR_OUI_BYTE0,
|
||||
&oui_bytes[0]);
|
||||
hw->phy.ops.read_i2c_eeprom(hw,
|
||||
IXGBE_SFF_VENDOR_OUI_BYTE1,
|
||||
&oui_bytes[1]);
|
||||
hw->phy.ops.read_i2c_eeprom(hw,
|
||||
IXGBE_SFF_VENDOR_OUI_BYTE2,
|
||||
&oui_bytes[2]);
|
||||
|
||||
vendor_oui =
|
||||
((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
|
||||
(oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
|
||||
(oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
|
||||
|
||||
switch (vendor_oui) {
|
||||
case IXGBE_SFF_VENDOR_OUI_TYCO:
|
||||
if (transmission_media &
|
||||
IXGBE_SFF_TWIN_AX_CAPABLE)
|
||||
hw->phy.type = ixgbe_phy_tw_tyco;
|
||||
break;
|
||||
case IXGBE_SFF_VENDOR_OUI_FTL:
|
||||
hw->phy.type = ixgbe_phy_sfp_ftl;
|
||||
break;
|
||||
case IXGBE_SFF_VENDOR_OUI_AVAGO:
|
||||
hw->phy.type = ixgbe_phy_sfp_avago;
|
||||
break;
|
||||
default:
|
||||
if (transmission_media &
|
||||
IXGBE_SFF_TWIN_AX_CAPABLE)
|
||||
hw->phy.type = ixgbe_phy_tw_unknown;
|
||||
else
|
||||
hw->phy.type = ixgbe_phy_sfp_unknown;
|
||||
break;
|
||||
}
|
||||
}
|
||||
status = IXGBE_SUCCESS;
|
||||
}
|
||||
|
||||
out:
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
|
||||
* @hw: pointer to hardware structure
|
||||
* @list_offset: offset to the SFP ID list
|
||||
* @data_offset: offset to the SFP data block
|
||||
*
|
||||
* Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
|
||||
* so it returns the offsets to the phy init sequence block.
|
||||
**/
|
||||
s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
|
||||
u16 *list_offset,
|
||||
u16 *data_offset)
|
||||
{
|
||||
u16 sfp_id;
|
||||
|
||||
if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
|
||||
return IXGBE_ERR_SFP_NOT_SUPPORTED;
|
||||
|
||||
if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
|
||||
return IXGBE_ERR_SFP_NOT_PRESENT;
|
||||
|
||||
if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
|
||||
(hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
|
||||
return IXGBE_ERR_SFP_NOT_SUPPORTED;
|
||||
|
||||
/* Read offset to PHY init contents */
|
||||
hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
|
||||
|
||||
if ((!*list_offset) || (*list_offset == 0xFFFF))
|
||||
return IXGBE_ERR_PHY;
|
||||
|
||||
/* Shift offset to first ID word */
|
||||
(*list_offset)++;
|
||||
|
||||
/*
|
||||
* Find the matching SFP ID in the EEPROM
|
||||
* and program the init sequence
|
||||
*/
|
||||
hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
|
||||
|
||||
while (sfp_id != IXGBE_PHY_INIT_END_NL) {
|
||||
if (sfp_id == hw->phy.sfp_type) {
|
||||
(*list_offset)++;
|
||||
hw->eeprom.ops.read(hw, *list_offset, data_offset);
|
||||
if ((!*data_offset) || (*data_offset == 0xFFFF)) {
|
||||
DEBUGOUT("SFP+ module not supported\n");
|
||||
return IXGBE_ERR_SFP_NOT_SUPPORTED;
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
(*list_offset) += 2;
|
||||
if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
|
||||
return IXGBE_ERR_PHY;
|
||||
}
|
||||
}
|
||||
|
||||
if (sfp_id == IXGBE_PHY_INIT_END_NL) {
|
||||
DEBUGOUT("No matching SFP+ module found\n");
|
||||
return IXGBE_ERR_SFP_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
return IXGBE_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
@ -36,6 +36,52 @@
|
||||
#define _IXGBE_PHY_H_
|
||||
|
||||
#include "ixgbe_type.h"
|
||||
#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0
|
||||
|
||||
/* EEPROM byte offsets */
|
||||
#define IXGBE_SFF_IDENTIFIER 0x0
|
||||
#define IXGBE_SFF_IDENTIFIER_SFP 0x3
|
||||
#define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25
|
||||
#define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26
|
||||
#define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27
|
||||
#define IXGBE_SFF_1GBE_COMP_CODES 0x6
|
||||
#define IXGBE_SFF_10GBE_COMP_CODES 0x3
|
||||
#define IXGBE_SFF_TRANSMISSION_MEDIA 0x9
|
||||
|
||||
/* Bitmasks */
|
||||
#define IXGBE_SFF_TWIN_AX_CAPABLE 0x80
|
||||
#define IXGBE_SFF_1GBASESX_CAPABLE 0x1
|
||||
#define IXGBE_SFF_10GBASESR_CAPABLE 0x10
|
||||
#define IXGBE_SFF_10GBASELR_CAPABLE 0x20
|
||||
#define IXGBE_I2C_EEPROM_READ_MASK 0x100
|
||||
#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3
|
||||
#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
|
||||
#define IXGBE_I2C_EEPROM_STATUS_PASS 0x1
|
||||
#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
|
||||
#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
|
||||
|
||||
/* Bit-shift macros */
|
||||
#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 12
|
||||
#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 8
|
||||
#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 4
|
||||
|
||||
/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
|
||||
#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
|
||||
#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500
|
||||
#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
|
||||
|
||||
/* I2C SDA and SCL timing parameters for standard mode */
|
||||
#define IXGBE_I2C_T_HD_STA 4
|
||||
#define IXGBE_I2C_T_LOW 5
|
||||
#define IXGBE_I2C_T_HIGH 4
|
||||
#define IXGBE_I2C_T_SU_STA 5
|
||||
#define IXGBE_I2C_T_HD_DATA 5
|
||||
#define IXGBE_I2C_T_SU_DATA 1
|
||||
#define IXGBE_I2C_T_RISE 1
|
||||
#define IXGBE_I2C_T_FALL 1
|
||||
#define IXGBE_I2C_T_SU_STO 4
|
||||
#define IXGBE_I2C_T_BUF 5
|
||||
|
||||
|
||||
s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
|
||||
bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
|
||||
@ -60,4 +106,9 @@ s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
|
||||
s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
|
||||
u16 *firmware_version);
|
||||
|
||||
s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
|
||||
u16 *list_offset,
|
||||
u16 *data_offset);
|
||||
#endif /* _IXGBE_PHY_H_ */
|
||||
|
||||
@ -41,12 +41,15 @@
|
||||
#define IXGBE_INTEL_VENDOR_ID 0x8086
|
||||
|
||||
/* Device IDs */
|
||||
#define IXGBE_DEV_ID_82598 0x10B6
|
||||
#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
|
||||
#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
|
||||
#define IXGBE_DEV_ID_82598AT 0x10C8
|
||||
#define IXGBE_DEV_ID_82598AT_DUAL_PORT 0x10D7
|
||||
#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
|
||||
#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
|
||||
#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
|
||||
#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
|
||||
#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
|
||||
#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
|
||||
|
||||
/* General Registers */
|
||||
@ -78,7 +81,9 @@
|
||||
#define IXGBE_EIMC 0x00888
|
||||
#define IXGBE_EIAC 0x00810
|
||||
#define IXGBE_EIAM 0x00890
|
||||
#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : (0x012300 + ((_i) * 4)))
|
||||
#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
|
||||
(0x012300 + ((_i) * 4)))
|
||||
#define IXGBE_EITR_ITR_INT_MASK 0x00000FFF
|
||||
#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
|
||||
#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
|
||||
#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
|
||||
@ -94,12 +99,18 @@
|
||||
#define IXGBE_TFCS 0x0CE00
|
||||
|
||||
/* Receive DMA Registers */
|
||||
#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : (0x0D000 + ((_i - 64) * 0x40)))
|
||||
#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : (0x0D004 + ((_i - 64) * 0x40)))
|
||||
#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : (0x0D008 + ((_i - 64) * 0x40)))
|
||||
#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : (0x0D010 + ((_i - 64) * 0x40)))
|
||||
#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : (0x0D018 + ((_i - 64) * 0x40)))
|
||||
#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : (0x0D028 + ((_i - 64) * 0x40)))
|
||||
#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
|
||||
(0x0D000 + ((_i - 64) * 0x40)))
|
||||
#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
|
||||
(0x0D004 + ((_i - 64) * 0x40)))
|
||||
#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
|
||||
(0x0D008 + ((_i - 64) * 0x40)))
|
||||
#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
|
||||
(0x0D010 + ((_i - 64) * 0x40)))
|
||||
#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
|
||||
(0x0D018 + ((_i - 64) * 0x40)))
|
||||
#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
|
||||
(0x0D028 + ((_i - 64) * 0x40)))
|
||||
/*
|
||||
* Split and Replication Receive Control Registers
|
||||
* 00-15 : 0x02100 + n*4
|
||||
@ -118,8 +129,7 @@
|
||||
#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
|
||||
(((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
|
||||
(0x0D00C + ((_i - 64) * 0x40))))
|
||||
#define IXGBE_RDRXCTL 0x02F00
|
||||
#define IXGBE_RDRXCTRL_RSC_PUSH 0x80
|
||||
#define IXGBE_RDRXCTL 0x02F00
|
||||
#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
|
||||
/* 8 of these 0x03C00 - 0x03C1C */
|
||||
#define IXGBE_RXCTRL 0x03000
|
||||
@ -129,12 +139,17 @@
|
||||
/* Receive Registers */
|
||||
#define IXGBE_RXCSUM 0x05000
|
||||
#define IXGBE_RFCTL 0x05008
|
||||
#define IXGBE_DRECCCTL 0x02F08
|
||||
#define IXGBE_DRECCCTL_DISABLE 0
|
||||
/* Multicast Table Array - 128 entries */
|
||||
#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
|
||||
#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : (0x0A200 + ((_i) * 8)))
|
||||
#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : (0x0A204 + ((_i) * 8)))
|
||||
#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
|
||||
(0x0A200 + ((_i) * 8)))
|
||||
#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
|
||||
(0x0A204 + ((_i) * 8)))
|
||||
/* Packet split receive type */
|
||||
#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : (0x0EA00 + ((_i) * 4)))
|
||||
#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
|
||||
(0x0EA00 + ((_i) * 4)))
|
||||
/* array of 4096 1-bit vlan filters */
|
||||
#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
|
||||
/*array of 4096 4-bit vlan vmdq indices */
|
||||
@ -164,7 +179,7 @@
|
||||
|
||||
#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
|
||||
#define IXGBE_TIPG 0x0CB00
|
||||
#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) *0x04)) /* 8 of these */
|
||||
#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
|
||||
#define IXGBE_MNGTXMAP 0x0CD10
|
||||
#define IXGBE_TIPG_FIBER_DEFAULT 3
|
||||
#define IXGBE_TXPBSIZE_SHIFT 10
|
||||
@ -176,11 +191,72 @@
|
||||
#define IXGBE_IPAV 0x05838
|
||||
#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
|
||||
#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
|
||||
|
||||
#define IXGBE_WUPL 0x05900
|
||||
#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
|
||||
#define IXGBE_FHFT 0x09000 /* Flex host filter table 9000-93FC */
|
||||
#define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */
|
||||
#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) /* Ext Flexible Host
|
||||
* Filter Table */
|
||||
|
||||
/* Music registers */
|
||||
#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
|
||||
#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
|
||||
|
||||
/* Each Flexible Filter is at most 128 (0x80) bytes in length */
|
||||
#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
|
||||
#define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
|
||||
#define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
|
||||
|
||||
/* Definitions for power management and wakeup registers */
|
||||
/* Wake Up Control */
|
||||
#define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */
|
||||
#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
|
||||
#define IXGBE_WUC_ADVD3WUC 0x00000010 /* D3Cold wake up cap. enable*/
|
||||
|
||||
/* Wake Up Filter Control */
|
||||
#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
|
||||
#define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
|
||||
#define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
|
||||
#define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
|
||||
#define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
|
||||
#define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
|
||||
#define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
|
||||
#define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
|
||||
#define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */
|
||||
|
||||
#define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
|
||||
#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
|
||||
#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
|
||||
#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
|
||||
#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
|
||||
#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
|
||||
#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
|
||||
#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
|
||||
#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
|
||||
#define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all 6 wakeup filters*/
|
||||
#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
|
||||
|
||||
/* Wake Up Status */
|
||||
#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
|
||||
#define IXGBE_WUS_MAG IXGBE_WUFC_MAG
|
||||
#define IXGBE_WUS_EX IXGBE_WUFC_EX
|
||||
#define IXGBE_WUS_MC IXGBE_WUFC_MC
|
||||
#define IXGBE_WUS_BC IXGBE_WUFC_BC
|
||||
#define IXGBE_WUS_ARP IXGBE_WUFC_ARP
|
||||
#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
|
||||
#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
|
||||
#define IXGBE_WUS_MNG IXGBE_WUFC_MNG
|
||||
#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
|
||||
#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
|
||||
#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
|
||||
#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
|
||||
#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
|
||||
#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
|
||||
#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
|
||||
|
||||
/* Wake Up Packet Length */
|
||||
#define IXGBE_WUPL_LENGTH_MASK 0xFFFF
|
||||
|
||||
/* DCB registers */
|
||||
#define IXGBE_RMCS 0x03D00
|
||||
#define IXGBE_DPMCS 0x07F40
|
||||
#define IXGBE_PDPMCS 0x0CD00
|
||||
@ -192,33 +268,6 @@
|
||||
#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
|
||||
#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
|
||||
|
||||
/* LinkSec (MacSec) Registers */
|
||||
#define IXGBE_LSECTXCTRL 0x08A04
|
||||
#define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */
|
||||
#define IXGBE_LSECTXSCH 0x08A0C /* SCI High */
|
||||
#define IXGBE_LSECTXSA 0x08A10
|
||||
#define IXGBE_LSECTXPN0 0x08A14
|
||||
#define IXGBE_LSECTXPN1 0x08A18
|
||||
#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
|
||||
#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
|
||||
#define IXGBE_LSECRXCTRL 0x08F04
|
||||
#define IXGBE_LSECRXSCL 0x08F08
|
||||
#define IXGBE_LSECRXSCH 0x08F0C
|
||||
#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
|
||||
#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
|
||||
#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
|
||||
|
||||
/* IpSec Registers */
|
||||
#define IXGBE_IPSTXIDX 0x08900
|
||||
#define IXGBE_IPSTXSALT 0x08904
|
||||
#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
|
||||
#define IXGBE_IPSRXIDX 0x08E00
|
||||
#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
|
||||
#define IXGBE_IPSRXSPI 0x08E14
|
||||
#define IXGBE_IPSRXIPIDX 0x08E18
|
||||
#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
|
||||
#define IXGBE_IPSRXSALT 0x08E2C
|
||||
#define IXGBE_IPSRXMOD 0x08E30
|
||||
|
||||
|
||||
/* Stats registers */
|
||||
@ -274,8 +323,9 @@
|
||||
#define IXGBE_BPTC 0x040F4
|
||||
#define IXGBE_XEC 0x04120
|
||||
|
||||
#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) /* 16 of these */
|
||||
#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : (0x08600 + ((_i) * 4)))
|
||||
#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
|
||||
#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
|
||||
(0x08600 + ((_i) * 4)))
|
||||
|
||||
#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
|
||||
#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
|
||||
@ -419,6 +469,7 @@
|
||||
#define IXGBE_MHADD_MFS_SHIFT 16
|
||||
|
||||
/* Extended Device Control */
|
||||
#define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */
|
||||
#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */
|
||||
#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
|
||||
#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
|
||||
@ -479,12 +530,14 @@
|
||||
#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
|
||||
#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
|
||||
|
||||
|
||||
/* Device Type definitions for new protocol MDIO commands */
|
||||
#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
|
||||
#define IXGBE_MDIO_PCS_DEV_TYPE 0x3
|
||||
#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
|
||||
#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
|
||||
#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
|
||||
#define IXGBE_TWINAX_DEV 1
|
||||
|
||||
#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
|
||||
|
||||
@ -505,6 +558,10 @@
|
||||
#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */
|
||||
#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */
|
||||
|
||||
#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
|
||||
#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
|
||||
#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
|
||||
|
||||
/* MII clause 22/28 definitions */
|
||||
#define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800
|
||||
|
||||
@ -520,10 +577,23 @@
|
||||
#define TN1010_PHY_ID 0x00A19410
|
||||
#define TNX_FW_REV 0xB
|
||||
#define QT2022_PHY_ID 0x0043A400
|
||||
#define ATH_PHY_ID 0x03429050
|
||||
|
||||
/* PHY Types */
|
||||
#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
|
||||
|
||||
/* Special PHY Init Routine */
|
||||
#define IXGBE_PHY_INIT_OFFSET_NL 0x002B
|
||||
#define IXGBE_PHY_INIT_END_NL 0xFFFF
|
||||
#define IXGBE_CONTROL_MASK_NL 0xF000
|
||||
#define IXGBE_DATA_MASK_NL 0x0FFF
|
||||
#define IXGBE_CONTROL_SHIFT_NL 12
|
||||
#define IXGBE_DELAY_NL 0
|
||||
#define IXGBE_DATA_NL 1
|
||||
#define IXGBE_CONTROL_NL 0x000F
|
||||
#define IXGBE_CONTROL_EOL_NL 0x0FFF
|
||||
#define IXGBE_CONTROL_SOL_NL 0x0000
|
||||
|
||||
/* General purpose Interrupt Enable */
|
||||
#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
|
||||
#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */
|
||||
@ -585,8 +655,8 @@
|
||||
#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
|
||||
|
||||
/* FCRTL Bit Masks */
|
||||
#define IXGBE_FCRTL_XONE 0x80000000 /* bit 31, XON enable */
|
||||
#define IXGBE_FCRTH_FCEN 0x80000000 /* Rx Flow control enable */
|
||||
#define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */
|
||||
#define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */
|
||||
|
||||
/* PAP bit masks*/
|
||||
#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
|
||||
@ -596,8 +666,8 @@
|
||||
/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
|
||||
#define IXGBE_RMCS_RAC 0x00000004
|
||||
#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
|
||||
#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority flow control ena */
|
||||
#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority flow control ena */
|
||||
#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */
|
||||
#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */
|
||||
#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
|
||||
|
||||
|
||||
@ -694,17 +764,20 @@
|
||||
#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
|
||||
|
||||
/* STATUS Bit Masks */
|
||||
#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
|
||||
#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
|
||||
#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
|
||||
#define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/
|
||||
#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
|
||||
|
||||
#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
|
||||
#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
|
||||
|
||||
/* ESDP Bit Masks */
|
||||
#define IXGBE_ESDP_SDP4 0x00000001 /* SDP4 Data Value */
|
||||
#define IXGBE_ESDP_SDP5 0x00000002 /* SDP5 Data Value */
|
||||
#define IXGBE_ESDP_SDP1 0x00000001
|
||||
#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
|
||||
#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
|
||||
#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
|
||||
#define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */
|
||||
#define IXGBE_ESDP_SDP5_DIR 0x00000008 /* SDP5 IO direction */
|
||||
#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
|
||||
|
||||
/* LEDCTL Bit Masks */
|
||||
#define IXGBE_LED_IVRT_BASE 0x00000040
|
||||
@ -727,6 +800,7 @@
|
||||
#define IXGBE_LED_OFF 0xF
|
||||
|
||||
/* AUTOC Bit Masks */
|
||||
#define IXGBE_AUTOC_KX4_KX_SUPP 0xC0000000
|
||||
#define IXGBE_AUTOC_KX4_SUPP 0x80000000
|
||||
#define IXGBE_AUTOC_KX_SUPP 0x40000000
|
||||
#define IXGBE_AUTOC_PAUSE 0x30000000
|
||||
@ -738,16 +812,16 @@
|
||||
#define IXGBE_AUTOC_AN_RESTART 0x00001000
|
||||
#define IXGBE_AUTOC_FLU 0x00000001
|
||||
#define IXGBE_AUTOC_LMS_SHIFT 13
|
||||
#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
|
||||
#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
|
||||
#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
|
||||
#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
|
||||
#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
|
||||
#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
|
||||
#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
|
||||
#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
|
||||
#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
|
||||
#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
|
||||
#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
|
||||
#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
|
||||
#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
|
||||
#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
|
||||
|
||||
#define IXGBE_AUTOC_1G_PMA_PMD 0x00000200
|
||||
#define IXGBE_AUTOC_10G_PMA_PMD 0x00000180
|
||||
#define IXGBE_AUTOC_1G_PMA_PMD 0x00000200
|
||||
#define IXGBE_AUTOC_10G_PMA_PMD 0x00000180
|
||||
#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
|
||||
#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
|
||||
#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
|
||||
@ -1019,6 +1093,7 @@
|
||||
#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
|
||||
#define IXGBE_RXD_CFI_SHIFT 12
|
||||
|
||||
|
||||
/* SRRCTL bit definitions */
|
||||
#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
|
||||
#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
|
||||
@ -1062,7 +1137,6 @@
|
||||
#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
|
||||
#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
|
||||
#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
|
||||
|
||||
/* Masks to determine if packets should be dropped due to frame errors */
|
||||
#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
|
||||
IXGBE_RXD_ERR_CE | \
|
||||
@ -1094,13 +1168,18 @@
|
||||
|
||||
#ifndef __le16
|
||||
/* Little Endian defines */
|
||||
#define __le8 u8
|
||||
#define __le16 u16
|
||||
#define __le32 u32
|
||||
#define __le64 u64
|
||||
|
||||
#endif
|
||||
#ifndef __be16
|
||||
/* Big Endian defines */
|
||||
#define __be16 u16
|
||||
#define __be32 u32
|
||||
#define __be64 u64
|
||||
|
||||
#endif
|
||||
|
||||
/* Transmit Descriptor - Legacy */
|
||||
struct ixgbe_legacy_tx_desc {
|
||||
@ -1109,15 +1188,15 @@ struct ixgbe_legacy_tx_desc {
|
||||
__le32 data;
|
||||
struct {
|
||||
__le16 length; /* Data buffer length */
|
||||
__le8 cso; /* Checksum offset */
|
||||
__le8 cmd; /* Descriptor control */
|
||||
u8 cso; /* Checksum offset */
|
||||
u8 cmd; /* Descriptor control */
|
||||
} flags;
|
||||
} lower;
|
||||
union {
|
||||
__le32 data;
|
||||
struct {
|
||||
__le8 status; /* Descriptor status */
|
||||
__le8 css; /* Checksum start */
|
||||
u8 status; /* Descriptor status */
|
||||
u8 css; /* Checksum start */
|
||||
__le16 vlan;
|
||||
} fields;
|
||||
} upper;
|
||||
@ -1142,8 +1221,8 @@ struct ixgbe_legacy_rx_desc {
|
||||
__le64 buffer_addr; /* Address of the descriptor's data buffer */
|
||||
__le16 length; /* Length of data DMAed into data buffer */
|
||||
__le16 csum; /* Packet checksum */
|
||||
__le8 status; /* Descriptor status */
|
||||
__le8 errors; /* Descriptor Errors */
|
||||
u8 status; /* Descriptor status */
|
||||
u8 errors; /* Descriptor Errors */
|
||||
__le16 vlan;
|
||||
};
|
||||
|
||||
@ -1221,7 +1300,7 @@ struct ixgbe_adv_tx_context_desc {
|
||||
#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
|
||||
#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
|
||||
#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
|
||||
#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* Req requires Markers and CRC */
|
||||
#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/
|
||||
#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
|
||||
#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
|
||||
|
||||
@ -1236,6 +1315,22 @@ typedef u32 ixgbe_link_speed;
|
||||
#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
|
||||
IXGBE_LINK_SPEED_10GB_FULL)
|
||||
|
||||
/* Physical layer type */
|
||||
typedef u32 ixgbe_physical_layer;
|
||||
#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
|
||||
#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
|
||||
#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
|
||||
#define IXGBE_PHYSICAL_LAYER_100BASE_T 0x0004
|
||||
#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
|
||||
#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
|
||||
#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
|
||||
#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
|
||||
#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
|
||||
#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
|
||||
#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
|
||||
#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
|
||||
|
||||
|
||||
enum ixgbe_eeprom_type {
|
||||
ixgbe_eeprom_uninitialized = 0,
|
||||
ixgbe_eeprom_spi,
|
||||
@ -1253,9 +1348,32 @@ enum ixgbe_phy_type {
|
||||
ixgbe_phy_tn,
|
||||
ixgbe_phy_qt,
|
||||
ixgbe_phy_xaui,
|
||||
ixgbe_phy_nl,
|
||||
ixgbe_phy_tw_tyco,
|
||||
ixgbe_phy_tw_unknown,
|
||||
ixgbe_phy_sfp_avago,
|
||||
ixgbe_phy_sfp_ftl,
|
||||
ixgbe_phy_sfp_unknown,
|
||||
ixgbe_phy_generic
|
||||
};
|
||||
|
||||
/*
|
||||
* SFP+ module type IDs:
|
||||
*
|
||||
* ID Module Type
|
||||
* =============
|
||||
* 0 SFP_DA_CU
|
||||
* 1 SFP_SR
|
||||
* 2 SFP_LR
|
||||
*/
|
||||
enum ixgbe_sfp_type {
|
||||
ixgbe_sfp_type_da_cu = 0,
|
||||
ixgbe_sfp_type_sr = 1,
|
||||
ixgbe_sfp_type_lr = 2,
|
||||
ixgbe_sfp_type_not_present = 0xFFFE,
|
||||
ixgbe_sfp_type_unknown = 0xFFFF
|
||||
};
|
||||
|
||||
enum ixgbe_media_type {
|
||||
ixgbe_media_type_unknown = 0,
|
||||
ixgbe_media_type_fiber,
|
||||
@ -1265,7 +1383,7 @@ enum ixgbe_media_type {
|
||||
};
|
||||
|
||||
/* Flow Control Settings */
|
||||
enum ixgbe_fc_type {
|
||||
enum ixgbe_fc_mode {
|
||||
ixgbe_fc_none = 0,
|
||||
ixgbe_fc_rx_pause,
|
||||
ixgbe_fc_tx_pause,
|
||||
@ -1321,6 +1439,8 @@ struct ixgbe_bus_info {
|
||||
enum ixgbe_bus_speed speed;
|
||||
enum ixgbe_bus_width width;
|
||||
enum ixgbe_bus_type type;
|
||||
|
||||
u16 func;
|
||||
};
|
||||
|
||||
/* Flow control parameters */
|
||||
@ -1330,8 +1450,8 @@ struct ixgbe_fc_info {
|
||||
u16 pause_time; /* Flow Control Pause timer */
|
||||
bool send_xon; /* Flow control send XON */
|
||||
bool strict_ieee; /* Strict IEEE mode */
|
||||
enum ixgbe_fc_type type; /* Type of flow control */
|
||||
enum ixgbe_fc_type original_type;
|
||||
enum ixgbe_fc_mode current_mode; /* FC mode in effect */
|
||||
enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
|
||||
};
|
||||
|
||||
/* Statistics counters collected by the MAC */
|
||||
@ -1415,9 +1535,11 @@ struct ixgbe_mac_operations {
|
||||
s32 (*start_hw)(struct ixgbe_hw *);
|
||||
s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
|
||||
enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
|
||||
u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
|
||||
s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
|
||||
s32 (*stop_adapter)(struct ixgbe_hw *);
|
||||
s32 (*get_bus_info)(struct ixgbe_hw *);
|
||||
void (*set_lan_id)(struct ixgbe_hw *);
|
||||
s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
|
||||
s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
|
||||
|
||||
@ -1457,6 +1579,7 @@ struct ixgbe_mac_operations {
|
||||
|
||||
struct ixgbe_phy_operations {
|
||||
s32 (*identify)(struct ixgbe_hw *);
|
||||
s32 (*identify_sfp)(struct ixgbe_hw *);
|
||||
s32 (*reset)(struct ixgbe_hw *);
|
||||
s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
|
||||
s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
|
||||
@ -1465,6 +1588,10 @@ struct ixgbe_phy_operations {
|
||||
bool);
|
||||
s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
|
||||
s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
|
||||
s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
|
||||
s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
|
||||
s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
|
||||
s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
|
||||
};
|
||||
|
||||
struct ixgbe_eeprom_info {
|
||||
@ -1488,9 +1615,10 @@ struct ixgbe_mac_info {
|
||||
u32 max_rx_queues;
|
||||
u32 link_attach_type;
|
||||
u32 link_mode_select;
|
||||
u32 link_kx4_kx_supp;
|
||||
bool link_settings_loaded;
|
||||
bool autoneg;
|
||||
bool autoneg_failed;
|
||||
bool autoneg_succeeded;
|
||||
};
|
||||
|
||||
struct ixgbe_phy_info {
|
||||
@ -1498,11 +1626,13 @@ struct ixgbe_phy_info {
|
||||
enum ixgbe_phy_type type;
|
||||
u32 addr;
|
||||
u32 id;
|
||||
enum ixgbe_sfp_type sfp_type;
|
||||
u32 revision;
|
||||
enum ixgbe_media_type media_type;
|
||||
bool reset_disable;
|
||||
ixgbe_autoneg_advertised autoneg_advertised;
|
||||
bool autoneg_wait_to_complete;
|
||||
bool multispeed_fiber;
|
||||
};
|
||||
|
||||
struct ixgbe_hw {
|
||||
@ -1523,7 +1653,7 @@ struct ixgbe_hw {
|
||||
};
|
||||
|
||||
#define ixgbe_call_func(hw, func, params, error) \
|
||||
(func != NULL) ? func params: error
|
||||
(func != NULL) ? func params : error
|
||||
|
||||
/* Error Codes */
|
||||
#define IXGBE_SUCCESS 0
|
||||
@ -1544,6 +1674,9 @@ struct ixgbe_hw {
|
||||
#define IXGBE_ERR_RESET_FAILED -15
|
||||
#define IXGBE_ERR_SWFW_SYNC -16
|
||||
#define IXGBE_ERR_PHY_ADDR_INVALID -17
|
||||
#define IXGBE_ERR_I2C -18
|
||||
#define IXGBE_ERR_SFP_NOT_SUPPORTED -19
|
||||
#define IXGBE_ERR_SFP_NOT_PRESENT -20
|
||||
#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
|
||||
|
||||
#define UNREFERENCED_PARAMETER(_p)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user