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Add two tunables to ignore certain firmware-assigned resources. These

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are mostly useful for debugging.
- hw.pci.clear_bars ignores all firmware-assigned ranges for BARs when
  set.
- hw.pci.clear_pcib ignores all firmware-assigned ranges for PCI-PCI
  bridge I/O windows when set.

MFC after:	1 week
This commit is contained in:
jhb 2014-02-05 20:52:12 +00:00
parent 3c6a6e899a
commit 6260fba82d
2 changed files with 25 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
sys/dev/pci/pci.c
View File

@ -332,6 +332,11 @@ SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN,
Disable this if you depend on BIOS emulation of USB devices, that is\n\
you use USB devices (like keyboard or mouse) but do not load USB drivers");
static int pci_clear_bars;
TUNABLE_INT("hw.pci.clear_bars", &pci_clear_bars);
SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0,
"Ignore firmware-assigned resources for BARs.");
static int
pci_has_quirk(uint32_t devid, int quirk)
{
@ -2851,7 +2856,7 @@ pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl,
flags = RF_ALIGNMENT_LOG2(mapsize);
if (prefetch)
flags |= RF_PREFETCHABLE;
if (basezero || base == pci_mapbase(testval)) {
if (basezero || base == pci_mapbase(testval) || pci_clear_bars) {
start = 0; /* Let the parent decide. */
end = ~0ul;
} else {

19
sys/dev/pci/pci_pci.c
View File

@ -103,6 +103,12 @@ DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL);
#ifdef NEW_PCIB
SYSCTL_DECL(_hw_pci);
static int pci_clear_pcib;
TUNABLE_INT("hw.pci.clear_pcib", &pci_clear_pcib);
SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0,
"Clear firmware-assigned resources for PCI-PCI bridge I/O windows.");
/*
* Is a resource from a child device sub-allocated from one of our
@ -416,6 +422,19 @@ pcib_probe_windows(struct pcib_softc *sc)
dev = sc->dev;
if (pci_clear_pcib) {
pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2);
pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1);
pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2);
pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2);
pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2);
pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4);
pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2);
pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4);
}
/* Determine if the I/O port window is implemented. */
val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
if (val == 0) {