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Give devices lots of time to settle around programming BARs and command

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registers.  Without this, the settings do not seem to stick for Atheros NICs in
the PCI slot of the Lanner MR-320.
This commit is contained in:
Juli Mallett 2010-09-27 20:35:40 +00:00
parent 7b9a15f73c
commit 62f24c60ef
1 changed files with 4 additions and 0 deletions
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4
sys/mips/cavium/octopci.c
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@ -659,6 +659,8 @@ octopci_init_device(device_t dev, unsigned b, unsigned s, unsigned f, unsigned s
command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
octopci_write_config(dev, b, s, f, PCIR_COMMAND, command, 1);
DELAY(10000);
/* Program BARs. */
switch (hdrtype & PCIM_HDRTYPE) {
case PCIM_HDRTYPE_NORMAL:
@ -685,6 +687,8 @@ octopci_init_device(device_t dev, unsigned b, unsigned s, unsigned f, unsigned s
/* Enable whatever facilities the BARs require. */
octopci_write_config(dev, b, s, f, PCIR_COMMAND, command, 1);
DELAY(10000);
/*
* Set cache line size. On Octeon it should be 128 bytes,
* but according to Linux some Intel bridges have trouble