Add support for 'C'-compressed ISA extension to DTrace FBT provider.
Approved by: re (kib) Sponsored by: DARPA, AFRL
This commit is contained in:
br
parent
545428e18d
commit
639c5f49ef
@ -2496,12 +2496,11 @@ extern void dtrace_helpers_destroy(proc_t *);
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#elif defined(__riscv)
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#define SD_RA_SP_MASK 0x01fff07f
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#define SD_RA_SP 0x00113023
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#define DTRACE_INVOP_SD 1
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#define DTRACE_INVOP_RET 2
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#define DTRACE_INVOP_NOP 3
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#define DTRACE_INVOP_C_SDSP 2
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#define DTRACE_INVOP_RET 3
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#define DTRACE_INVOP_C_RET 4
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#define DTRACE_INVOP_NOP 5
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#endif
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@ -19,7 +19,7 @@
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*
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* CDDL HEADER END
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*
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* Portions Copyright 2016 Ruslan Bukin <br@bsdpad.com>
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* Portions Copyright 2016-2018 Ruslan Bukin <br@bsdpad.com>
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*
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* $FreeBSD$
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*
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@ -42,8 +42,8 @@ __FBSDID("$FreeBSD$");
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#include <sys/dtrace_impl.h>
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#include <sys/dtrace_bsd.h>
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#include <machine/vmparam.h>
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#include <machine/encoding.h>
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#include <machine/riscvreg.h>
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#include <machine/riscv_opcode.h>
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#include <machine/clock.h>
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#include <machine/frame.h>
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#include <machine/trap.h>
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@ -77,7 +77,6 @@ dtrace_invop(uintptr_t addr, struct trapframe *frame, uintptr_t eax)
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return (0);
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}
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void
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dtrace_invop_add(int (*func)(uintptr_t, struct trapframe *, uintptr_t))
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{
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@ -237,30 +236,59 @@ dtrace_probe_error(dtrace_state_t *state, dtrace_epid_t epid, int which,
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(uintptr_t)which, (uintptr_t)fault, (uintptr_t)fltoffs);
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}
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static int
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match_opcode(uint32_t insn, int match, int mask)
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{
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if (((insn ^ match) & mask) == 0)
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return (1);
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return (0);
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}
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static int
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dtrace_invop_start(struct trapframe *frame)
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{
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int data, invop, reg, update_sp;
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register_t arg1, arg2;
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register_t *sp;
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uint32_t uimm;
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uint32_t imm;
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InstFmt i;
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int offs;
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int tmp;
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int invop;
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invop = dtrace_invop(frame->tf_sepc, frame, frame->tf_sepc);
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if (invop == RISCV_INSN_RET) {
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if (match_opcode(invop, (MATCH_SD | RS2_RA | RS1_SP),
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(MASK_SD | RS2_MASK | RS1_MASK))) {
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/* Non-compressed store of ra to sp */
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imm = (invop >> 7) & 0x1f;
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imm |= ((invop >> 25) & 0x7f) << 5;
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sp = (register_t *)((uint8_t *)frame->tf_sp + imm);
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*sp = frame->tf_ra;
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frame->tf_sepc += INSN_SIZE;
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return (0);
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}
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if (match_opcode(invop, (MATCH_JALR | (X_RA << RS1_SHIFT)),
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(MASK_JALR | RD_MASK | RS1_MASK | IMM_MASK))) {
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/* Non-compressed ret */
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frame->tf_sepc = frame->tf_ra;
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return (0);
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}
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if ((invop & SD_RA_SP_MASK) == SD_RA_SP) {
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i.word = invop;
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imm = i.SType.imm0_4 | (i.SType.imm5_11 << 5);
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sp = (register_t *)((uint8_t *)frame->tf_sp + imm);
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if (match_opcode(invop, (MATCH_C_SDSP | RS2_C_RA),
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(MASK_C_SDSP | RS2_C_MASK))) {
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/* 'C'-compressed store of ra to sp */
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uimm = ((invop >> 10) & 0x7) << 3;
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uimm |= ((invop >> 7) & 0x7) << 6;
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sp = (register_t *)((uint8_t *)frame->tf_sp + uimm);
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*sp = frame->tf_ra;
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frame->tf_sepc += INSN_SIZE;
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frame->tf_sepc += INSN_C_SIZE;
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return (0);
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}
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if (match_opcode(invop, (MATCH_C_JR | (X_RA << RD_SHIFT)),
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(MASK_C_JR | RD_MASK))) {
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/* 'C'-compressed ret */
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frame->tf_sepc = frame->tf_ra;
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return (0);
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}
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@ -21,7 +21,7 @@
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* Portions Copyright 2006-2008 John Birrell jb@freebsd.org
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* Portions Copyright 2013 Justin Hibbits jhibbits@freebsd.org
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* Portions Copyright 2013 Howard Su howardsu@freebsd.org
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* Portions Copyright 2016 Ruslan Bukin <br@bsdpad.com>
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* Portions Copyright 2016-2018 Ruslan Bukin <br@bsdpad.com>
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*
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* $FreeBSD$
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*/
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@ -37,10 +37,12 @@
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#include <sys/dtrace.h>
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#include <machine/riscvreg.h>
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#include <machine/encoding.h>
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#include "fbt.h"
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#define FBT_PATCHVAL (RISCV_INSN_BREAK)
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#define FBT_C_PATCHVAL MATCH_C_EBREAK
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#define FBT_PATCHVAL MATCH_EBREAK
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#define FBT_ENTRY "entry"
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#define FBT_RETURN "return"
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@ -73,8 +75,62 @@ void
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fbt_patch_tracepoint(fbt_probe_t *fbt, fbt_patchval_t val)
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{
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*fbt->fbtp_patchpoint = val;
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cpu_icache_sync_range((vm_offset_t)fbt->fbtp_patchpoint, 4);
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switch(fbt->fbtp_patchval) {
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case FBT_C_PATCHVAL:
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*(uint16_t *)fbt->fbtp_patchpoint = (uint16_t)val;
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cpu_icache_sync_range((vm_offset_t)fbt->fbtp_patchpoint, 2);
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break;
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case FBT_PATCHVAL:
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*fbt->fbtp_patchpoint = val;
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cpu_icache_sync_range((vm_offset_t)fbt->fbtp_patchpoint, 4);
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break;
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};
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}
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static int
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match_opcode(uint32_t insn, int match, int mask)
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{
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if (((insn ^ match) & mask) == 0)
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return (1);
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return (0);
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}
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static int
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check_c_ret(uint32_t **instr)
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{
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uint16_t *instr1;
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int i;
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for (i = 0; i < 2; i++) {
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instr1 = (uint16_t *)(*instr) + i;
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if (match_opcode(*instr1, (MATCH_C_JR | (X_RA << RD_SHIFT)),
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(MASK_C_JR | RD_MASK))) {
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*instr = (uint32_t *)instr1;
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return (1);
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}
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}
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return (0);
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}
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static int
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check_c_sdsp(uint32_t **instr)
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{
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uint16_t *instr1;
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int i;
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for (i = 0; i < 2; i++) {
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instr1 = (uint16_t *)(*instr) + i;
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if (match_opcode(*instr1, (MATCH_C_SDSP | RS2_C_RA),
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(MASK_C_SDSP | RS2_C_MASK))) {
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*instr = (uint32_t *)instr1;
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return (1);
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}
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}
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return (0);
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}
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int
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@ -85,6 +141,8 @@ fbt_provide_module_function(linker_file_t lf, int symindx,
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uint32_t *instr, *limit;
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const char *name;
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char *modname;
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int patchval;
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int rval;
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modname = opaque;
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name = symval->name;
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@ -98,8 +156,20 @@ fbt_provide_module_function(linker_file_t lf, int symindx,
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/* Look for sd operation */
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for (; instr < limit; instr++) {
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if ((*instr & SD_RA_SP_MASK) == SD_RA_SP)
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/* Look for a non-compressed store of ra to sp */
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if (match_opcode(*instr, (MATCH_SD | RS2_RA | RS1_SP),
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(MASK_SD | RS2_MASK | RS1_MASK))) {
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rval = DTRACE_INVOP_SD;
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patchval = FBT_PATCHVAL;
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break;
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}
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/* Look for a 'C'-compressed store of ra to sp. */
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if (check_c_sdsp(&instr)) {
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rval = DTRACE_INVOP_C_SDSP;
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patchval = FBT_C_PATCHVAL;
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break;
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}
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}
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if (instr >= limit)
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@ -113,8 +183,8 @@ fbt_provide_module_function(linker_file_t lf, int symindx,
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fbt->fbtp_ctl = lf;
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fbt->fbtp_loadcnt = lf->loadcnt;
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fbt->fbtp_savedval = *instr;
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fbt->fbtp_patchval = FBT_PATCHVAL;
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fbt->fbtp_rval = DTRACE_INVOP_SD;
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fbt->fbtp_patchval = patchval;
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fbt->fbtp_rval = rval;
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fbt->fbtp_symindx = symindx;
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fbt->fbtp_hashnext = fbt_probetab[FBT_ADDR2NDX(instr)];
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@ -125,8 +195,20 @@ fbt_provide_module_function(linker_file_t lf, int symindx,
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retfbt = NULL;
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again:
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for (; instr < limit; instr++) {
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if (*instr == RISCV_INSN_RET)
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/* Look for non-compressed return */
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if (match_opcode(*instr, (MATCH_JALR | (X_RA << RS1_SHIFT)),
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(MASK_JALR | RD_MASK | RS1_MASK | IMM_MASK))) {
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rval = DTRACE_INVOP_RET;
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patchval = FBT_PATCHVAL;
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break;
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}
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/* Look for 'C'-compressed return */
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if (check_c_ret(&instr)) {
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rval = DTRACE_INVOP_C_RET;
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patchval = FBT_C_PATCHVAL;
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break;
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}
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}
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if (instr >= limit)
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@ -150,9 +232,9 @@ again:
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fbt->fbtp_ctl = lf;
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fbt->fbtp_loadcnt = lf->loadcnt;
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fbt->fbtp_symindx = symindx;
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fbt->fbtp_rval = DTRACE_INVOP_RET;
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fbt->fbtp_rval = rval;
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fbt->fbtp_savedval = *instr;
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fbt->fbtp_patchval = FBT_PATCHVAL;
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fbt->fbtp_patchval = patchval;
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fbt->fbtp_hashnext = fbt_probetab[FBT_ADDR2NDX(instr)];
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fbt_probetab[FBT_ADDR2NDX(instr)] = fbt;
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@ -88,6 +88,15 @@ device vtnet # VirtIO Ethernet device
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device virtio_blk # VirtIO Block device
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device virtio_mmio # VirtIO MMIO bus
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# DTrace support
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# device dtrace
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# device dtrace_profile
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# device dtrace_sdt
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# device dtrace_fbt
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# device dtrace_systrace
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# device dtrace_prototype
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# device dtraceall
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# Serial (COM) ports
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device uart # Generic UART driver
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device uart_ns8250 # ns8250-type UART driver
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@ -1,116 +0,0 @@
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/*-
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* Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Portions of this software were developed by the University of Cambridge
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* Computer Laboratory as part of the CTSRD Project, with support from the
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* UK Higher Education Innovation Fund (HEIF).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_RISCV_OPCODE_H_
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#define _MACHINE_RISCV_OPCODE_H_
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/*
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* Define the instruction formats and opcode values for the
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* RISC-V instruction set.
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*/
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#include <machine/endian.h>
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/*
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* Define the instruction formats.
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*/
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typedef union {
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unsigned word;
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struct {
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unsigned opcode: 7;
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unsigned rd: 5;
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unsigned funct3: 3;
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unsigned rs1: 5;
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unsigned rs2: 5;
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unsigned funct7: 7;
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} RType;
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struct {
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unsigned opcode: 7;
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unsigned rd: 5;
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unsigned funct3: 3;
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unsigned rs1: 5;
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unsigned rs2: 6;
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unsigned funct7: 6;
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} R2Type;
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struct {
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unsigned opcode: 7;
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unsigned rd: 5;
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unsigned funct3: 3;
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unsigned rs1: 5;
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unsigned imm: 12;
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} IType;
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struct {
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unsigned opcode: 7;
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unsigned imm0_4: 5;
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unsigned funct3: 3;
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unsigned rs1: 5;
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unsigned rs2: 5;
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unsigned imm5_11: 7;
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} SType;
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struct {
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unsigned opcode: 7;
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unsigned imm11: 1;
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unsigned imm1_4: 4;
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unsigned funct3: 3;
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unsigned rs1: 5;
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unsigned rs2: 5;
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unsigned imm5_10: 6;
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unsigned imm12: 1;
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} SBType;
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struct {
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unsigned opcode: 7;
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unsigned rd: 5;
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unsigned imm12_31: 20;
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} UType;
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struct {
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unsigned opcode: 7;
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unsigned rd: 5;
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unsigned imm12_19: 8;
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unsigned imm11: 1;
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unsigned imm1_10: 10;
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unsigned imm20: 1;
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} UJType;
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} InstFmt;
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#define RISCV_OPCODE(r) (r & 0x7f)
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#endif /* !_MACHINE_RISCV_OPCODE_H_ */
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@ -157,10 +157,31 @@
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#define XLEN 8
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#define INSN_SIZE 4
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#define INSN_C_SIZE 2
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#define RISCV_INSN_NOP 0x00000013
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#define RISCV_INSN_BREAK 0x00100073
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#define RISCV_INSN_RET 0x00008067
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#define X_RA 1
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#define X_SP 2
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#define X_GP 3
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#define X_TP 4
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#define X_T0 5
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#define X_T1 6
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#define X_T2 7
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#define X_T3 28
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#define RD_SHIFT 7
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#define RD_MASK (0x1f << RD_SHIFT)
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#define RS1_SHIFT 15
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#define RS1_MASK (0x1f << RS1_SHIFT)
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#define RS1_SP (X_SP << RS1_SHIFT)
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#define RS2_SHIFT 20
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#define RS2_MASK (0x1f << RS2_SHIFT)
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#define RS2_RA (X_RA << RS2_SHIFT)
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#define IMM_SHIFT 20
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#define IMM_MASK (0xfff << IMM_SHIFT)
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#define RS2_C_SHIFT 2
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#define RS2_C_MASK (0x1f << RS2_C_SHIFT)
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#define RS2_C_RA (X_RA << RS2_C_SHIFT)
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#define CSR_ZIMM(val) \
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(__builtin_constant_p(val) && ((u_long)(val) < 32))
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