Import a basic implementation of the restartable atomic sequences to provide
atomic operations to userland (this is OK for UP only, but SMP is still so far away).
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cognet
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0eff5864a9
commit
64c6be3ab3
@ -113,6 +113,21 @@
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add r0, sp, #(4*13); /* Adjust the stack pointer */ \
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stmia r0, {r13-r14}^; /* Push the user mode registers */ \
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mov r0, r0; /* NOP for previous instruction */ \
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ldr r5, =0xe0000004; /* Check if there's any RAS */ \
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ldr r3, [r5]; \
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cmp r3, #0; /* Is the update needed ? */ \
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beq 1f; \
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ldr lr, [r0, #16]; \
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ldr r1, =0xe0000008; \
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ldr r4, [r1]; /* Get the end of the RAS */ \
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mov r2, #0; /* Reset the magic addresses */ \
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str r2, [r5]; \
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str r2, [r1]; \
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cmp lr, r3; /* Were we in the RAS ? */ \
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blt 1f; \
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cmp lr, r4; \
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strlt r3, [r0, #16]; /* Yes, update the pc */ \
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1: \
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mrs r0, spsr_all; /* Put the SPSR on the stack */ \
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str r0, [sp, #-4]!
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@ -168,7 +183,6 @@
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#define AST_LOCALS ;\
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.Lcurthread: ;\
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.word _C_LABEL(__pcpu) + PC_CURTHREAD
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#endif /* LOCORE */
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@ -71,6 +71,9 @@
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: "cc" ); \
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} while(0)
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#define ARM_RAS_START 0xe0000004
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#define ARM_RAS_END 0xe0000008
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static __inline uint32_t
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__swp(uint32_t val, volatile uint32_t *ptr)
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{
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@ -80,39 +83,162 @@ __swp(uint32_t val, volatile uint32_t *ptr)
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}
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#define atomic_op(v, op, p) ({ \
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uint32_t e, r, s; \
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for (e = *(volatile uint32_t *)p;; e = r) { \
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s = e op v; \
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r = __swp(s, p); \
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if (r == e) \
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break; \
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} \
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e; \
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})
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#ifdef _KERNEL
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static __inline void
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atomic_set_32(volatile uint32_t *address, uint32_t setmask)
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{
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atomic_op(setmask, |, address);
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__with_interrupts_disabled(*address |= setmask);
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}
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static __inline void
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atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
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{
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atomic_op(clearmask, &~, address);
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__with_interrupts_disabled(*address &= ~clearmask);
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}
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static __inline u_int32_t
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atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
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{
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int ret;
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__with_interrupts_disabled(
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{
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if (*p == cmpval) {
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*p = newval;
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ret = 1;
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} else {
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ret = 0;
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}
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});
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return (ret);
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}
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static __inline void
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atomic_add_32(volatile u_int32_t *p, u_int32_t val)
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{
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__with_interrupts_disabled(*p += val);
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}
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static __inline void
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atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
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{
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__with_interrupts_disabled(*p -= val);
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}
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#else /* !_KERNEL */
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static __inline u_int32_t
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atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
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{
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register int done, ras_start;
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__asm __volatile("1:\n"
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"mov %0, #0xe0000008\n"
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"adr %1, 2f\n"
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"str %1, [%0]\n"
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"adr %1, 1b\n"
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"mov %0, #0xe0000004\n"
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"str %1, [%0]\n"
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"ldr %1, [%2]\n"
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"cmp %1, %3\n"
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"streq %4, [%2]\n"
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"2:\n"
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"moveq %1, #1\n"
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"movne %1, #0\n"
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: "=r" (ras_start), "=r" (done)
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,"+r" (p), "+r" (cmpval), "+r" (newval));
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return (done);
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}
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static __inline void
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atomic_add_32(volatile u_int32_t *p, u_int32_t val)
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{
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int ras_start, start;
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__asm __volatile("1:\n"
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"mov %0, #0xe0000008\n"
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"adr %1, 2f\n"
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"str %1, [%0]\n"
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"adr %1, 1b\n"
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"mov %0, #0xe0000004\n"
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"str %1, [%0]\n"
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"ldr %1, [%2]\n"
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"add %1, %1, %3\n"
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"str %1, [%2]\n"
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"2:\n"
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: "=r" (ras_start), "=r" (start), "+r" (p), "+r" (val));
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}
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static __inline void
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atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
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{
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int ras_start, start;
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__asm __volatile("1:\n"
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"mov %0, #0xe0000008\n"
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"adr %1, 2f\n"
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"str %1, [%0]\n"
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"adr %1, 1b\n"
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"mov %0, #0xe0000004\n"
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"str %1, [%0]\n"
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"ldr %1, [%2]\n"
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"sub %1, %1, %3\n"
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"str %1, [%2]\n"
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"2:\n"
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: "=r" (ras_start), "=r" (start), "+r" (p), "+r" (val));
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}
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static __inline void
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atomic_set_32(volatile uint32_t *address, uint32_t setmask)
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{
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int ras_start, start;
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__asm __volatile("1:\n"
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"mov %0, #0xe0000008\n"
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"adr %1, 2f\n"
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"str %1, [%0]\n"
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"adr %1, 1b\n"
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"mov %0, #0xe0000004\n"
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"str %1, [%0]\n"
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"ldr %1, [%2]\n"
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"orr %1, %1, %3\n"
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"str %1, [%2]\n"
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"2:\n"
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: "=r" (ras_start), "=r" (start), "+r" (address), "+r" (setmask));
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}
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static __inline void
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atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
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{
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int ras_start, start;
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__asm __volatile("1:\n"
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"mov %0, #0xe0000008\n"
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"adr %1, 2f\n"
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"str %1, [%0]\n"
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"adr %1, 1b\n"
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"mov %0, #0xe0000004\n"
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"str %1, [%0]\n"
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"ldr %1, [%2]\n"
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"bic %1, %1, %3\n"
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"str %1, [%2]\n"
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"2:\n"
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: "=r" (ras_start), "=r" (start), "+r" (address), "+r" (clearmask));
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}
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#endif /* _KERNEL */
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static __inline int
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atomic_load_32(volatile uint32_t *v)
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{
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return (atomic_op(0, +, v));
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return (*v);
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}
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static __inline void
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atomic_store_32(volatile uint32_t *dst, uint32_t src)
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{
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__swp(src, dst);
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*dst = src;
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}
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static __inline uint32_t
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@ -122,36 +248,6 @@ atomic_readandclear_32(volatile u_int32_t *p)
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return (__swp(0, p));
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}
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#ifdef _KERNEL
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static __inline u_int32_t
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atomic_cmpset_32(volatile u_int32_t *p, u_int32_t cmpval, u_int32_t newval)
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{
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int done;
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__with_interrupts_disabled(
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{
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if (*p == cmpval) {
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*p = newval;
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done = 1;
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} else
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done = 0;
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});
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return (done);
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}
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#endif
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static __inline void
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atomic_add_32(volatile u_int32_t *p, u_int32_t val)
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{
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atomic_op(val, +, p);
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}
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static __inline void
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atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
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{
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atomic_op(val, -, p);
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}
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#undef __with_interrupts_disabled
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#endif /* _LOCORE */
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