From 6815909abdaace1f8f70678873c763deec36223a Mon Sep 17 00:00:00 2001 From: Andrew Turner Date: Mon, 4 Jan 2021 13:25:45 +0000 Subject: [PATCH] Move the PMC overflow count to make it per-CPU Virtual PMCs could be running on multiple CPUs so this needs to be a per-CPU value. Submitted by: rwatson (earlier version) Reviewed by: gnn Sponsored by: Innovate UK Differential Revision: https://reviews.freebsd.org/D27973 --- sys/dev/hwpmc/hwpmc_arm64.c | 8 ++++---- sys/dev/hwpmc/hwpmc_armv7.c | 8 ++++---- sys/sys/pmc.h | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/sys/dev/hwpmc/hwpmc_arm64.c b/sys/dev/hwpmc/hwpmc_arm64.c index 15ea4f892ed0..49375219a485 100644 --- a/sys/dev/hwpmc/hwpmc_arm64.c +++ b/sys/dev/hwpmc/hwpmc_arm64.c @@ -215,12 +215,12 @@ arm64_read_pmc(int cpu, int ri, pmc_value_t *v) /* Clear Overflow Flag */ WRITE_SPECIALREG(pmovsclr_el0, reg); if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) - pm->pm_overflowcnt++; + pm->pm_pcpu_state[cpu].pps_overflowcnt++; /* Reread counter in case we raced. */ tmp = arm64_pmcn_read(ri); } - tmp += 0x100000000llu * pm->pm_overflowcnt; + tmp += 0x100000000llu * pm->pm_pcpu_state[cpu].pps_overflowcnt; intr_restore(s); PMCDBG2(MDP, REA, 2, "arm64-read id=%d -> %jd", ri, tmp); @@ -249,7 +249,7 @@ arm64_write_pmc(int cpu, int ri, pmc_value_t v) PMCDBG3(MDP, WRI, 1, "arm64-write cpu=%d ri=%d v=%jx", cpu, ri, v); - pm->pm_overflowcnt = v >> 32; + pm->pm_pcpu_state[cpu].pps_overflowcnt = v >> 32; arm64_pmcn_write(ri, v); return 0; @@ -373,7 +373,7 @@ arm64_intr(struct trapframe *tf) retval = 1; /* Found an interrupting PMC. */ if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { - pm->pm_overflowcnt += 1; + pm->pm_pcpu_state[cpu].pps_overflowcnt += 1; continue; } diff --git a/sys/dev/hwpmc/hwpmc_armv7.c b/sys/dev/hwpmc/hwpmc_armv7.c index bf38b06cfb56..84a983bbc69c 100644 --- a/sys/dev/hwpmc/hwpmc_armv7.c +++ b/sys/dev/hwpmc/hwpmc_armv7.c @@ -192,12 +192,12 @@ armv7_read_pmc(int cpu, int ri, pmc_value_t *v) /* Clear Overflow Flag */ cp15_pmovsr_set(reg); if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) - pm->pm_overflowcnt += 1; + pm->pm_pcpu_state[cpu].pps_overflowcnt++; /* Reread counter in case we raced. */ tmp = armv7_pmcn_read(ri, pm->pm_md.pm_armv7.pm_armv7_evsel); } - tmp += 0x100000000llu * pm->pm_overflowcnt; + tmp += 0x100000000llu * pm->pm_pcpu_state[cpu].pps_overflowcnt; intr_restore(s); PMCDBG2(MDP, REA, 2, "armv7-read id=%d -> %jd", ri, tmp); @@ -226,7 +226,7 @@ armv7_write_pmc(int cpu, int ri, pmc_value_t v) PMCDBG3(MDP, WRI, 1, "armv7-write cpu=%d ri=%d v=%jx", cpu, ri, v); - pm->pm_overflowcnt = v >> 32; + pm->pm_pcpu_state[cpu].pps_overflowcnt = v >> 32; if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES) cp15_pmccntr_set(v); else @@ -363,7 +363,7 @@ armv7_intr(struct trapframe *tf) retval = 1; /* Found an interrupting PMC. */ if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { - pm->pm_overflowcnt += 1; + pm->pm_pcpu_state[cpu].pps_overflowcnt += 1; continue; } if (pm->pm_state != PMC_STATE_RUNNING) diff --git a/sys/sys/pmc.h b/sys/sys/pmc.h index 997357c4a031..1486c7aa91c7 100644 --- a/sys/sys/pmc.h +++ b/sys/sys/pmc.h @@ -729,6 +729,7 @@ struct pmc_target { * */ struct pmc_pcpu_state { + uint32_t pps_overflowcnt; /* count overflow interrupts */ uint8_t pps_stalled; uint8_t pps_cpustate; } __aligned(CACHE_LINE_SIZE); @@ -773,7 +774,6 @@ struct pmc { struct pmc_owner *pm_owner; /* owner thread state */ counter_u64_t pm_runcount; /* #cpus currently on */ enum pmc_state pm_state; /* current PMC state */ - uint32_t pm_overflowcnt; /* count overflow interrupts */ /* * The PMC ID field encodes the row-index for the PMC, its