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Bring over interrupt mitigation changes from ath9k.

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* The existing interrupt mitigation code didn't mitigate anything - the
  per-packet TX/RX interrupts are still occuring. It's possible this
  worked for the AR5416 but not any later chipsets; I'll investigate and
  update as needed.

* Set both the RX and TX threshold registers whilst I'm at it.

This is verified to work on the AR9220 and AR9160. I'm leaving it off
by default in case it's truely broken, but I need to have it enabled
when doing 11n testing or interrupt loads exceed 10,000 interrupts/sec.
This commit is contained in:
Adrian Chadd 2011-03-25 00:03:21 +00:00
parent 89b172238a
commit 6893df4146
2 changed files with 20 additions and 10 deletions
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27
sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c
View File

@ -194,6 +194,23 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
mask = ints & HAL_INT_COMMON;
mask2 = 0;
#ifdef AR5416_INT_MITIGATION
/*
* Overwrite default mask if Interrupt mitigation
* is specified for AR5416
*/
mask = ints & HAL_INT_COMMON;
if (ints & HAL_INT_TX)
mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
if (ints & HAL_INT_RX)
mask |= AR_IMR_RXERR | AR_IMR_RXMINTR | AR_IMR_RXINTM;
if (ints & HAL_INT_TX) {
if (ahp->ah_txErrInterruptMask)
mask |= AR_IMR_TXERR;
if (ahp->ah_txEolInterruptMask)
mask |= AR_IMR_TXEOL;
}
#else
if (ints & HAL_INT_TX) {
if (ahp->ah_txOkInterruptMask)
mask |= AR_IMR_TXOK;
@ -206,16 +223,6 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
}
if (ints & HAL_INT_RX)
mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC;
#ifdef AR5416_INT_MITIGATION
/*
* Overwrite default mask if Interrupt mitigation
* is specified for AR5416
*/
mask = ints & HAL_INT_COMMON;
if (ints & HAL_INT_TX)
mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
if (ints & HAL_INT_RX)
mask |= AR_IMR_RXERR | AR_IMR_RXMINTR | AR_IMR_RXINTM;
#endif
if (ints & (HAL_INT_BMISC)) {
mask |= AR_IMR_BCNMISC;

3
sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
View File

@ -307,8 +307,11 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
#ifdef AR5416_INT_MITIGATION
OS_REG_WRITE(ah, AR_MIRT, 0);
OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
OS_REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
OS_REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
#endif
ar5416InitBB(ah, chan);