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Since all generations of Intel CPUs have errata which causes hang on

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the cache line flush in the LAPIC page, keep direct map page covering
LAPIC mapped uncached.

To have the (incomplete) check for the LAPIC range in
pmap_invalidate_cache_range() working, lapic_paddr must be initialized
in x2APIC mode too.

Sponsored by:	The FreeBSD Foundation
MFC after:	2 months
This commit is contained in:
Konstantin Belousov 2015-02-27 11:13:46 +00:00
parent 851128b8de
commit 68c2f49379
1 changed files with 10 additions and 5 deletions
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15
sys/x86/x86/local_apic.c
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@ -388,16 +388,21 @@ native_lapic_init(vm_paddr_t addr)
int i, arat;
/*
* Enable x2APIC mode if possible, otherwise map the local
* APIC registers page.
* Enable x2APIC mode if possible. Map the local APIC
* registers page.
*
* Keep the LAPIC registers page mapped uncached for x2APIC
* mode too, to have direct map page attribute set to
* uncached. This is needed to work around CPU errata present
* on all Intel processors.
*/
KASSERT(trunc_page(addr) == addr,
("local APIC not aligned on a page boundary"));
lapic_paddr = addr;
lapic_map = pmap_mapdev(addr, PAGE_SIZE);
if (x2apic_mode) {
native_lapic_enable_x2apic();
} else {
lapic_paddr = addr;
lapic_map = pmap_mapdev(addr, PAGE_SIZE);
lapic_map = NULL;
}
/* Setup the spurious interrupt handler. */