[PowerPC64LE] Add LOAD_LR_NIA and RETURN_TO_NATIVE_ENDIAN defines.
* Add LOAD_LR_NIA define. This is preferred to "bl 1f; 1:" because it doesn't pollute the branch predictor. * Add magic sequence to return the CPU to the correct endianness after jumping to cross-endian code, similar to the sequence from Linux. Sponsored by: Tag1 Consulting, Inc.
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@ -194,6 +194,43 @@ name: \
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#define ASENTRY_NOPROF(y) _ENTRY(ASMNAME(y))
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#define ENTRY_NOPROF(y) _ENTRY(CNAME(y))
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/* Load NIA without affecting branch prediction */
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#define LOAD_LR_NIA bcl 20, 31, .+4
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/*
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* Magic sequence to return to native endian.
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* Overwrites r0 and r11.
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*
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* The encoding of the instruction "tdi 0, %r0, 0x48" in opposite endian
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* happens to be "b . + 8". This is useful because we can write a sequence
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* of instructions that can execute in either endian.
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*
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* Use a sequence of handcoded instructions that switches contexts to the
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* instruction following the sequence, but with the correct PSL_LE bit.
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*
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* The same sequence works for both BE and LE because the xori will flip
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* the bit to the other state, and the code only runs when running in the
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* wrong endian.
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*
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* This sequence is NMI-reentrant.
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*/
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#define RETURN_TO_NATIVE_ENDIAN \
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tdi 0, %r0, 0x48; /* Endian swapped: b . + 8 */\
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b 1f; /* Will fall through to here if correct */\
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.long 0xa600607d; /* mfmsr %r11 */\
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.long 0x00000038; /* li %r0, 0 */\
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.long 0x6401617d; /* mtmsrd %r0, 1 (L=1 EE,RI bits only) */\
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.long 0x01006b69; /* xori %r11, %r11, 0x1 (PSL_LE) */\
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.long 0xa602087c; /* mflr %r0 */\
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.long 0x05009f42; /* LOAD_LR_NIA */\
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.long 0xa6037b7d; /* 0: mtsrr1 %r11 */\
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.long 0xa602687d; /* mflr %r11 */\
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.long 0x18006b39; /* addi %r11, %r11, (1f - 0b) */\
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.long 0xa6037a7d; /* mtsrr0 %r11 */\
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.long 0xa603087c; /* mtlr %r0 */\
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.long 0x2400004c; /* rfid */\
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1: /* RETURN_TO_NATIVE_ENDIAN */
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#define ASMSTR .asciz
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#define RCSID(x) .text; .asciz x
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