K6-III CPUs are now case:d in the appropriate switch; also, in
print_AMD_info(), L2 internal cache is shown, as are AMD's special CPUID infos: CPU: AMD-K6(tm) 3D processor (350.81-MHz 586-class CPU) Origin = "AuthenticAMD" Id = 0x58c Stepping=12 Features=0x8021bf<FPU,VME,DE,PSE,TSC,MSR,MCE,CX8,PGE,MMX> AMD Features=0x808029bf<FPU,VME,DE,PSE,TSC,MSR,MCE,CX8,SYSCALL,PGE,MMX,3DNow!> PR: kern/12512 Submitted by: Louis A. Mamakos <louie@TransSys.COM>
This commit is contained in:
Brian Feldman
parent
439cce0e4b
commit
69c784af9f
@ -36,7 +36,7 @@
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* SUCH DAMAGE.
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*
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* from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
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* $Id: identcpu.c,v 1.64 1999/06/24 03:47:54 green Exp $
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* $Id: identcpu.c,v 1.65 1999/06/24 20:08:56 jlemon Exp $
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*/
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#include "opt_cpu.h"
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@ -295,6 +295,9 @@ printcpuinfo(void)
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case 0x580:
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strcat(cpu_model, "K6-2");
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break;
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case 0x590:
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strcat(cpu_model, "K6-III");
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break;
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default:
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strcat(cpu_model, "Unknown");
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break;
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@ -866,11 +869,51 @@ print_AMD_assoc(int i)
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static void
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print_AMD_info(void)
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{
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u_int regs[4];
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u_int regs[4], amd_maxregs;
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quad_t amd_whcr;
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do_cpuid(0x80000000, regs);
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if (regs[0] >= 0x80000005) {
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amd_maxregs = regs[0];
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if (amd_maxregs >= 0x80000001) {
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do_cpuid(0x80000001, regs);
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printf(" AMD Features=0x%b\n", regs[3],
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"\020" /* in hex */
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"\001FPU"
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"\002VME"
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"\003DE"
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"\004PSE"
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"\005TSC"
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"\006MSR"
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"\007<b6>"
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"\010MCE"
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"\011CX8"
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"\012<b9>"
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"\013<b10>"
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"\014SYSCALL"
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"\015<b12>"
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"\016PGE"
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"\017<b14>"
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"\020ICMOV"
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"\021FCMOV"
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"\022<b17>"
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"\023<b18>"
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"\024<b19>"
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"\025<b20>"
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"\026<b21>"
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"\027<b22>"
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"\030MMX"
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"\031<b24>"
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"\032<b25>"
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"\033<b26>"
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"\034<b27>"
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"\035<b28>"
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"\036<b29>"
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"\037<b30>"
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"\0403DNow!"
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);
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}
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if (amd_maxregs >= 0x80000005) {
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do_cpuid(0x80000005, regs);
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printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
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print_AMD_assoc(regs[1] >> 24);
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@ -884,12 +927,19 @@ print_AMD_info(void)
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printf(", %d bytes/line", regs[3] & 0xff);
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printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
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print_AMD_assoc((regs[3] >> 16) & 0xff);
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if (amd_maxregs >= 0x80000006) { /* K6-III only */
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do_cpuid(0x80000006, regs);
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printf("L2 internal cache: %d kbytes", regs[2] >> 16);
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printf(", %d bytes/line", regs[2] & 0xff);
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printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
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print_AMD_assoc((regs[2] >> 12) & 0x0f);
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}
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}
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if (((cpu_id & 0xf00) == 0x500)
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&& (((cpu_id & 0x0f0) > 0x80)
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|| (((cpu_id & 0x0f0) == 0x80)
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&& (cpu_id & 0x00f) > 0x07))) {
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/* K6-2(new core [Stepping 8-F]), K6-3 or later */
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/* K6-2(new core [Stepping 8-F]), K6-III or later */
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amd_whcr = rdmsr(0xc0000082);
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if (!(amd_whcr & (0x3ff << 22))) {
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printf("Write Allocate Disable\n");
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@ -36,7 +36,7 @@
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* SUCH DAMAGE.
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*
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* from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
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* $Id: identcpu.c,v 1.64 1999/06/24 03:47:54 green Exp $
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* $Id: identcpu.c,v 1.65 1999/06/24 20:08:56 jlemon Exp $
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*/
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#include "opt_cpu.h"
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@ -295,6 +295,9 @@ printcpuinfo(void)
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case 0x580:
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strcat(cpu_model, "K6-2");
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break;
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case 0x590:
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strcat(cpu_model, "K6-III");
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break;
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default:
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strcat(cpu_model, "Unknown");
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break;
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@ -866,11 +869,51 @@ print_AMD_assoc(int i)
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static void
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print_AMD_info(void)
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{
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u_int regs[4];
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u_int regs[4], amd_maxregs;
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quad_t amd_whcr;
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do_cpuid(0x80000000, regs);
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if (regs[0] >= 0x80000005) {
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amd_maxregs = regs[0];
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if (amd_maxregs >= 0x80000001) {
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do_cpuid(0x80000001, regs);
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printf(" AMD Features=0x%b\n", regs[3],
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"\020" /* in hex */
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"\001FPU"
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"\002VME"
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"\003DE"
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"\004PSE"
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"\005TSC"
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"\006MSR"
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"\007<b6>"
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"\010MCE"
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"\011CX8"
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"\012<b9>"
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"\013<b10>"
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"\014SYSCALL"
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"\015<b12>"
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"\016PGE"
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"\017<b14>"
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"\020ICMOV"
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"\021FCMOV"
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"\022<b17>"
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"\023<b18>"
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"\024<b19>"
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"\025<b20>"
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"\026<b21>"
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"\027<b22>"
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"\030MMX"
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"\031<b24>"
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"\032<b25>"
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"\033<b26>"
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"\034<b27>"
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"\035<b28>"
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"\036<b29>"
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"\037<b30>"
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"\0403DNow!"
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);
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}
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if (amd_maxregs >= 0x80000005) {
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do_cpuid(0x80000005, regs);
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printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
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print_AMD_assoc(regs[1] >> 24);
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@ -884,12 +927,19 @@ print_AMD_info(void)
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printf(", %d bytes/line", regs[3] & 0xff);
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printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
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print_AMD_assoc((regs[3] >> 16) & 0xff);
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if (amd_maxregs >= 0x80000006) { /* K6-III only */
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do_cpuid(0x80000006, regs);
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printf("L2 internal cache: %d kbytes", regs[2] >> 16);
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printf(", %d bytes/line", regs[2] & 0xff);
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printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
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print_AMD_assoc((regs[2] >> 12) & 0x0f);
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}
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}
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if (((cpu_id & 0xf00) == 0x500)
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&& (((cpu_id & 0x0f0) > 0x80)
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|| (((cpu_id & 0x0f0) == 0x80)
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&& (cpu_id & 0x00f) > 0x07))) {
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/* K6-2(new core [Stepping 8-F]), K6-3 or later */
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/* K6-2(new core [Stepping 8-F]), K6-III or later */
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amd_whcr = rdmsr(0xc0000082);
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if (!(amd_whcr & (0x3ff << 22))) {
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printf("Write Allocate Disable\n");
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