From 69e096c120ec1d9cd28d6d3e328d0e0bc5b5a968 Mon Sep 17 00:00:00 2001 From: imp Date: Fri, 11 Dec 2015 16:51:04 +0000 Subject: [PATCH] Correct the CONFIG0_VI value. According to http://www.t-es-t.hu/download/mips/md00090c.pdf this is bit 3 of the config0 word, not bit 2. This should fix virtually indexed caches (relatively new in the MIPS world, so no current platforms used this and current code just uses it as an optimization). It was causing false positives on newer platforms that default to large values for the kseg0 cache coherency attribute. Submitted by: Stanislav Galabov PR: 205249 --- sys/mips/include/cpuregs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/mips/include/cpuregs.h b/sys/mips/include/cpuregs.h index 54a9234069a8..a39f6a6a2688 100644 --- a/sys/mips/include/cpuregs.h +++ b/sys/mips/include/cpuregs.h @@ -524,7 +524,7 @@ #define MIPS_CONFIG0_MT_MASK 0x00000380 /* bits 9..7 MMU Type */ #define MIPS_CONFIG0_MT_SHIFT 7 #define MIPS_CONFIG0_BE 0x00008000 /* data is big-endian */ -#define MIPS_CONFIG0_VI 0x00000004 /* instruction cache is virtual */ +#define MIPS_CONFIG0_VI 0x00000008 /* instruction cache is virtual */ #define MIPS_CONFIG1_TLBSZ_MASK 0x7E000000 /* bits 30..25 # tlb entries minus one */ #define MIPS_CONFIG1_TLBSZ_SHIFT 25