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Allow setting access-width for UART registers.

Browse Source 
This is required for FDT's standard "reg-io-width" property
(similar to "reg-shift" property) found in many DTS files.

This fixes operation on Altera Arria 10 SOC Development Kit,
where standard ns8250 uart allows 4-byte access only.

Reviewed by:	kan, marcel
Sponsored by:	DARPA, AFRL
Differential Revision:	https://reviews.freebsd.org/D9785
This commit is contained in:
br 2017-02-27 20:08:42 +00:00
parent d947ed0ae7
commit 69f1ecb8f8
36 changed files with 109 additions and 45 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
sys/arm/at91/uart_bus_at91usart.c
View File

@ -104,7 +104,7 @@ usart_at91_probe(device_t dev)
sc->sc_class = &at91_usart_class;
if (sc->sc_class->uc_rclk == 0)
sc->sc_class->uc_rclk = at91_master_clock;
return (uart_bus_probe(dev, 0, 0, 0, device_get_unit(dev)));
return (uart_bus_probe(dev, 0, 0, 0, 0, device_get_unit(dev)));
}

2
sys/arm/cavium/cns11xx/uart_bus_ec.c
View File

@ -69,7 +69,7 @@ uart_ec_probe(device_t dev)
sc = device_get_softc(dev);
sc->sc_class = &uart_ns8250_class;
status = uart_bus_probe(dev, EC_UART_REGSHIFT, EC_UART_CLOCK, 0, 0);
status = uart_bus_probe(dev, EC_UART_REGSHIFT, 0, EC_UART_CLOCK, 0, 0);
return (status);
}

2
sys/arm/nvidia/tegra_uart.c
View File

@ -216,7 +216,7 @@ tegra_uart_probe(device_t dev)
device_printf(dev, "Cannot enable UART clock: %d\n", rv);
return (ENXIO);
}
return (uart_bus_probe(dev, shift, (int)freq, 0, 0));
return (uart_bus_probe(dev, shift, 0, (int)freq, 0, 0));
}
static int

2
sys/arm/xscale/i8134x/uart_bus_i81342.c
View File

@ -83,7 +83,7 @@ uart_i81342_probe(device_t dev)
0x40 | 0x10);
bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres);
err = uart_bus_probe(dev, 2, 33334000, 0, device_get_unit(dev));
err = uart_bus_probe(dev, 2, 0, 33334000, 0, device_get_unit(dev));
sc->sc_rxfifosz = sc->sc_txfifosz = 1;
return (err);
}

2
sys/arm/xscale/ixp425/uart_bus_ixp425.c
View File

@ -78,5 +78,5 @@ uart_ixp425_probe(device_t dev)
if (bootverbose)
device_printf(dev, "rclk %u\n", rclk);
return uart_bus_probe(dev, 0, rclk, 0, 0);
return uart_bus_probe(dev, 0, 0, rclk, 0, 0);
}

2
sys/arm/xscale/pxa/uart_bus_pxa.c
View File

@ -97,7 +97,7 @@ uart_pxa_probe(device_t dev)
sc = device_get_softc(dev);
sc->sc_class = &uart_ns8250_class;
return(uart_bus_probe(dev, 2, PXA2X0_COM_FREQ, 0, 0));
return(uart_bus_probe(dev, 2, 0, PXA2X0_COM_FREQ, 0, 0));
}
DRIVER_MODULE(uart, pxa, uart_pxa_driver, uart_devclass, 0, 0);

42
sys/dev/uart/uart.h
View File

@ -41,14 +41,48 @@ struct uart_bas {
u_int chan;
u_int rclk;
u_int regshft;
u_int regiowidth;
};
#define uart_regofs(bas, reg) ((reg) << (bas)->regshft)
#define uart_regiowidth(bas) ((bas)->regiowidth)
#define uart_getreg(bas, reg) \
bus_space_read_1((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
#define uart_setreg(bas, reg, value) \
bus_space_write_1((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
static inline uint32_t
uart_getreg(struct uart_bas *bas, int reg)
{
uint32_t ret;
switch (uart_regiowidth(bas)) {
case 4:
ret = bus_space_read_4(bas->bst, bas->bsh, uart_regofs(bas, reg));
break;
case 2:
ret = bus_space_read_2(bas->bst, bas->bsh, uart_regofs(bas, reg));
break;
default:
ret = bus_space_read_1(bas->bst, bas->bsh, uart_regofs(bas, reg));
break;
}
return (ret);
}
static inline void
uart_setreg(struct uart_bas *bas, int reg, int value)
{
switch (uart_regiowidth(bas)) {
case 4:
bus_space_write_4(bas->bst, bas->bsh, uart_regofs(bas, reg), value);
break;
case 2:
bus_space_write_2(bas->bst, bas->bsh, uart_regofs(bas, reg), value);
break;
default:
bus_space_write_1(bas->bst, bas->bsh, uart_regofs(bas, reg), value);
break;
}
}
/*
* XXX we don't know the length of the bus space address range in use by

3
sys/dev/uart/uart_bus.h
View File

@ -63,6 +63,7 @@ struct uart_class {
u_int uc_range; /* Bus space address range. */
u_int uc_rclk; /* Default rclk for this device. */
u_int uc_rshift; /* Default regshift for this device. */
u_int uc_riowidth; /* Default reg io width for this device. */
};
struct uart_softc {
@ -137,7 +138,7 @@ int uart_bus_detach(device_t dev);
int uart_bus_resume(device_t dev);
serdev_intr_t *uart_bus_ihand(device_t dev, int ipend);
int uart_bus_ipend(device_t dev);
int uart_bus_probe(device_t dev, int regshft, int rclk, int rid, int chan);
int uart_bus_probe(device_t dev, int regshft, int regiowidth, int rclk, int rid, int chan);
int uart_bus_sysdev(device_t dev);
void uart_sched_softih(struct uart_softc *, uint32_t);

4
sys/dev/uart/uart_bus_acpi.c
View File

@ -109,13 +109,13 @@ uart_acpi_probe(device_t dev)
#if defined(__i386__) || defined(__amd64__)
if (!ISA_PNP_PROBE(parent, dev, acpi_ns8250_ids)) {
sc->sc_class = &uart_ns8250_class;
return (uart_bus_probe(dev, 0, 0, 0, 0));
return (uart_bus_probe(dev, 0, 0, 0, 0, 0));
}
/* Add checks for non-ns8250 IDs here. */
#elif defined(__aarch64__)
if ((sc->sc_class = uart_acpi_find_device(dev)) != NULL)
return (uart_bus_probe(dev, 2, 0, 0, 0));
return (uart_bus_probe(dev, 2, 0, 0, 0, 0));
#endif
return (ENXIO);

2
sys/dev/uart/uart_bus_ebus.c
View File

@ -97,7 +97,7 @@ uart_ebus_probe(device_t dev)
return (ENXIO);
}
sc->sc_class = &uart_ns8250_class;
return (uart_bus_probe(dev, 0, 0, 0, 0));
return (uart_bus_probe(dev, 0, 0, 0, 0, 0));
}
return (ENXIO);

24
sys/dev/uart/uart_bus_fdt.c
View File

@ -90,6 +90,15 @@ uart_fdt_get_shift(phandle_t node, pcell_t *cell)
return (0);
}
int
uart_fdt_get_io_width(phandle_t node, pcell_t *cell)
{
if ((OF_getencprop(node, "reg-io-width", cell, sizeof(*cell))) <= 0)
return (-1);
return (0);
}
static uintptr_t
uart_fdt_find_device(device_t dev)
{
@ -154,14 +163,15 @@ uart_fdt_find_by_node(phandle_t node, int class_list)
int
uart_cpu_fdt_probe(struct uart_class **classp, bus_space_tag_t *bst,
bus_space_handle_t *bsh, int *baud, u_int *rclk, u_int *shiftp)
bus_space_handle_t *bsh, int *baud, u_int *rclk, u_int *shiftp,
u_int *iowidthp)
{
const char *propnames[] = {"stdout-path", "linux,stdout-path", "stdout",
"stdin-path", "stdin", NULL};
const char **name;
struct uart_class *class;
phandle_t node, chosen;
pcell_t br, clk, shift;
pcell_t br, clk, shift, iowidth;
char *cp;
int err;
@ -212,6 +222,9 @@ uart_cpu_fdt_probe(struct uart_class **classp, bus_space_tag_t *bst,
if (uart_fdt_get_shift(node, &shift) != 0)
shift = uart_getregshift(class);
if (uart_fdt_get_io_width(node, &iowidth) != 0)
iowidth = uart_getregiowidth(class);
if (OF_getencprop(node, "current-speed", &br, sizeof(br)) <= 0)
br = 0;
@ -223,6 +236,7 @@ uart_cpu_fdt_probe(struct uart_class **classp, bus_space_tag_t *bst,
*baud = br;
*rclk = clk;
*shiftp = shift;
*iowidthp = iowidth;
return (0);
}
@ -232,7 +246,7 @@ uart_fdt_probe(device_t dev)
{
struct uart_softc *sc;
phandle_t node;
pcell_t clock, shift;
pcell_t clock, shift, iowidth;
int err;
sc = device_get_softc(dev);
@ -250,8 +264,10 @@ uart_fdt_probe(device_t dev)
return (err);
if (uart_fdt_get_shift(node, &shift) != 0)
shift = uart_getregshift(sc->sc_class);
if (uart_fdt_get_io_width(node, &iowidth) != 0)
iowidth = uart_getregiowidth(sc->sc_class);
return (uart_bus_probe(dev, (int)shift, (int)clock, 0, 0));
return (uart_bus_probe(dev, (int)shift, (int)iowidth, (int)clock, 0, 0));
}
DRIVER_MODULE(uart, simplebus, uart_fdt_driver, uart_devclass, 0, 0);

2
sys/dev/uart/uart_bus_isa.c
View File

@ -165,7 +165,7 @@ uart_isa_probe(device_t dev)
/* Probe PnP _and_ non-PnP ns8250 here. */
sc->sc_class = &uart_ns8250_class;
return (uart_bus_probe(dev, 0, 0, 0, 0));
return (uart_bus_probe(dev, 0, 0, 0, 0, 0));
}
DRIVER_MODULE(uart, isa, uart_isa_driver, uart_devclass, 0, 0);

2
sys/dev/uart/uart_bus_pccard.c
View File

@ -93,7 +93,7 @@ uart_pccard_attach(device_t dev)
sc = device_get_softc(dev);
sc->sc_class = &uart_ns8250_class;
error = uart_bus_probe(dev, 0, 0, 0, 0);
error = uart_bus_probe(dev, 0, 0, 0, 0, 0);
if (error > 0)
return (error);
return (uart_bus_attach(dev));

2
sys/dev/uart/uart_bus_pci.c
View File

@ -201,7 +201,7 @@ uart_pci_probe(device_t dev)
return (ENXIO);
match:
result = uart_bus_probe(dev, id->regshft, id->rclk, id->rid, 0);
result = uart_bus_probe(dev, id->regshft, 0, id->rclk, id->rid, 0);
/* Bail out on error. */
if (result > 0)
return (result);

2
sys/dev/uart/uart_bus_puc.c
View File

@ -81,7 +81,7 @@ uart_puc_probe(device_t dev)
if (BUS_READ_IVAR(parent, dev, PUC_IVAR_CLOCK, &rclk))
rclk = 0;
return (uart_bus_probe(dev, 0, rclk, 0, 0));
return (uart_bus_probe(dev, 0, 0, rclk, 0, 0));
}
DRIVER_MODULE(uart, puc, uart_puc_driver, uart_devclass, 0, 0);

2
sys/dev/uart/uart_bus_scc.c
View File

@ -112,7 +112,7 @@ uart_scc_probe(device_t dev)
BUS_READ_IVAR(parent, dev, SCC_IVAR_REGSHFT, &rs))
return (ENXIO);
return (uart_bus_probe(dev, rs, cl, 0, ch));
return (uart_bus_probe(dev, rs, 0, cl, 0, ch));
}
DRIVER_MODULE(uart, scc, uart_scc_driver, uart_devclass, 0, 0);

9
sys/dev/uart/uart_core.c
View File

@ -256,6 +256,12 @@ uart_getregshift(struct uart_class *uc)
return ((uc != NULL) ? uc->uc_rshift : 0);
}
u_int
uart_getregiowidth(struct uart_class *uc)
{
return ((uc != NULL) ? uc->uc_riowidth : 0);
}
/*
* Schedule a soft interrupt. We do this on the 0 to !0 transition
* of the TTY pending interrupt status.
@ -485,7 +491,7 @@ uart_bus_sysdev(device_t dev)
}
int
uart_bus_probe(device_t dev, int regshft, int rclk, int rid, int chan)
uart_bus_probe(device_t dev, int regshft, int regiowidth, int rclk, int rid, int chan)
{
struct uart_softc *sc;
struct uart_devinfo *sysdev;
@ -543,6 +549,7 @@ uart_bus_probe(device_t dev, int regshft, int rclk, int rid, int chan)
sc->sc_bas.bst = rman_get_bustag(sc->sc_rres);
sc->sc_bas.chan = chan;
sc->sc_bas.regshft = regshft;
sc->sc_bas.regiowidth = regiowidth;
sc->sc_bas.rclk = (rclk == 0) ? sc->sc_class->uc_rclk : rclk;
SLIST_FOREACH(sysdev, &uart_sysdevs, next) {

1
sys/dev/uart/uart_cpu.h
View File

@ -80,6 +80,7 @@ const char *uart_getname(struct uart_class *);
struct uart_ops *uart_getops(struct uart_class *);
int uart_getrange(struct uart_class *);
u_int uart_getregshift(struct uart_class *);
u_int uart_getregiowidth(struct uart_class *);
void uart_add_sysdev(struct uart_devinfo *);

5
sys/dev/uart/uart_cpu_arm64.c
View File

@ -155,7 +155,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
struct uart_class *class;
bus_space_handle_t bsh;
bus_space_tag_t bst;
u_int rclk, shift;
u_int rclk, shift, iowidth;
int br, err;
/* Allow overriding the FDT using the environment. */
@ -174,7 +174,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
#ifdef FDT
if (err != 0) {
err = uart_cpu_fdt_probe(&class, &bst, &bsh, &br, &rclk,
&shift);
&shift, &iowidth);
}
#endif
if (err != 0)
@ -185,6 +185,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
*/
di->bas.chan = 0;
di->bas.regshft = shift;
di->bas.regiowidth = iowidth;
di->baudrate = br;
di->bas.rclk = rclk;
di->ops = uart_getops(class);

5
sys/dev/uart/uart_cpu_fdt.c
View File

@ -76,7 +76,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
struct uart_class *class;
bus_space_tag_t bst;
bus_space_handle_t bsh;
u_int shift, rclk;
u_int shift, iowidth, rclk;
int br, err;
/* Allow overriding the FDT using the environment. */
@ -88,7 +88,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
if (devtype != UART_DEV_CONSOLE)
return (ENXIO);
err = uart_cpu_fdt_probe(&class, &bst, &bsh, &br, &rclk, &shift);
err = uart_cpu_fdt_probe(&class, &bst, &bsh, &br, &rclk, &shift, &iowidth);
if (err != 0)
return (err);
@ -97,6 +97,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
*/
di->bas.chan = 0;
di->bas.regshft = shift;
di->bas.regiowidth = iowidth;
di->baudrate = br;
di->bas.rclk = rclk;
di->ops = uart_getops(class);

3
sys/dev/uart/uart_cpu_fdt.h
View File

@ -51,8 +51,9 @@ SET_DECLARE(uart_fdt_class_set, struct ofw_compat_data );
DATA_SET(uart_fdt_class_set, data)
int uart_cpu_fdt_probe(struct uart_class **, bus_space_tag_t *,
bus_space_handle_t *, int *, u_int *, u_int *);
bus_space_handle_t *, int *, u_int *, u_int *, u_int *);
int uart_fdt_get_clock(phandle_t node, pcell_t *cell);
int uart_fdt_get_shift(phandle_t node, pcell_t *cell);
int uart_fdt_get_io_width(phandle_t node, pcell_t *cell);
#endif /* _DEV_UART_CPU_FDT_H_ */

6
sys/dev/uart/uart_dev_snps.c
View File

@ -136,7 +136,7 @@ snps_probe(device_t dev)
struct snps_softc *sc;
struct uart_class *uart_class;
phandle_t node;
uint32_t shift, clock;
uint32_t shift, iowidth, clock;
uint64_t freq;
int error;
#ifdef EXT_RESOURCES
@ -159,6 +159,8 @@ snps_probe(device_t dev)
node = ofw_bus_get_node(dev);
if (OF_getencprop(node, "reg-shift", &shift, sizeof(shift)) <= 0)
shift = 0;
if (OF_getencprop(node, "reg-io-width", &iowidth, sizeof(iowidth)) <= 0)
iowidth = 1;
if (OF_getencprop(node, "clock-frequency", &clock, sizeof(clock)) <= 0)
clock = 0;
@ -200,7 +202,7 @@ snps_probe(device_t dev)
if (bootverbose && clock == 0)
device_printf(dev, "could not determine frequency\n");
error = uart_bus_probe(dev, (int)shift, (int)clock, 0, 0);
error = uart_bus_probe(dev, (int)shift, (int)iowidth, (int)clock, 0, 0);
if (error != 0)
return (error);

2
sys/mips/adm5120/uart_bus_adm5120.c
View File

@ -87,7 +87,7 @@ uart_adm5120_probe(device_t dev)
sc->sc_class = &uart_adm5120_uart_class;
bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
return (uart_bus_probe(dev, 0, 0, 0, 0));
return (uart_bus_probe(dev, 0, 0, 0, 0, 0));
}
DRIVER_MODULE(uart, obio, uart_adm5120_driver, uart_devclass, 0, 0);

2
sys/mips/alchemy/uart_bus_alchemy.c
View File

@ -81,7 +81,7 @@ uart_alchemy_probe(device_t dev)
sc->sc_class = &uart_ns8250_class;
bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
return (uart_bus_probe(dev, 0, 0, 0, 0));
return (uart_bus_probe(dev, 0, 0, 0, 0, 0));
}
DRIVER_MODULE(uart, obio, uart_alchemy_driver, uart_devclass, 0, 0);

2
sys/mips/atheros/ar531x/uart_bus_ar5315.c
View File

@ -83,7 +83,7 @@ uart_ar5315_probe(device_t dev)
sc->sc_bas.bst = mips_bus_space_generic;
sc->sc_bas.bsh = ar531x_uart_addr() + 3;
return (uart_bus_probe(dev, 2, freq, 0, 0));
return (uart_bus_probe(dev, 2, 0, freq, 0, 0));
}
DRIVER_MODULE(uart, apb, uart_ar5315_driver, uart_devclass, 0, 0);

2
sys/mips/atheros/uart_bus_ar71xx.c
View File

@ -83,7 +83,7 @@ uart_ar71xx_probe(device_t dev)
sc->sc_bas.bst = mips_bus_space_generic;
sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(AR71XX_UART_ADDR) + 3;
return (uart_bus_probe(dev, 2, freq, 0, 0));
return (uart_bus_probe(dev, 2, 0, freq, 0, 0));
}
#ifdef EARLY_PRINTF

2
sys/mips/atheros/uart_bus_ar933x.c
View File

@ -88,7 +88,7 @@ uart_ar933x_probe(device_t dev)
sc->sc_bas.bst = mips_bus_space_generic;
sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(AR71XX_UART_ADDR);
return (uart_bus_probe(dev, 2, freq, 0, 0));
return (uart_bus_probe(dev, 2, 0, freq, 0, 0));
}
/*

2
sys/mips/broadcom/uart_bus_chipc.c
View File

@ -61,7 +61,7 @@ uart_chipc_probe(device_t dev)
sc->sc_class = &uart_ns8250_class;
rclk = bcm_get_uart_rclk(bcm_get_platform());
return (uart_bus_probe(dev, 0, rclk, 0, 0));
return (uart_bus_probe(dev, 0, 0, rclk, 0, 0));
}
static device_method_t uart_chipc_methods[] = {

2
sys/mips/cavium/uart_bus_octeonusart.c
View File

@ -105,7 +105,7 @@ uart_octeon_probe(device_t dev)
if (bus_space_map(sc->sc_bas.bst, CVMX_MIO_UARTX_RBR(0),
uart_getrange(sc->sc_class), 0, &sc->sc_bas.bsh) != 0)
return (ENXIO);
return (uart_bus_probe(dev, sc->sc_bas.regshft, 0, 0, unit));
return (uart_bus_probe(dev, sc->sc_bas.regshft, 0, 0, 0, unit));
}
DRIVER_MODULE(uart, obio, uart_octeon_driver, uart_devclass, 0, 0);

2
sys/mips/idt/uart_bus_rc32434.c
View File

@ -94,7 +94,7 @@ uart_rc32434_probe(device_t dev)
sc->sc_bas.bst = mips_bus_space_generic;
sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(IDT_BASE_UART0);
return (uart_bus_probe(dev, 2, 330000000UL/2, 0, 0));
return (uart_bus_probe(dev, 2, 0, 330000000UL/2, 0, 0));
}
DRIVER_MODULE(uart, obio, uart_rc32434_driver, uart_devclass, 0, 0);

2
sys/mips/ingenic/jz4780_uart.c
View File

@ -179,7 +179,7 @@ jz4780_uart_probe(device_t dev)
device_printf(dev, "got UART clock: %lld\n", freq);
sc->ns8250_base.base.sc_class = (struct uart_class *)cd->ocd_data;
shift = jz4780_uart_get_shift(dev);
return (uart_bus_probe(dev, shift, (int)freq, 0, 0));
return (uart_bus_probe(dev, shift, 0, (int)freq, 0, 0));
}
static int

2
sys/mips/malta/uart_bus_maltausart.c
View File

@ -85,7 +85,7 @@ uart_malta_probe(device_t dev)
sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
sc->sc_bas.bst = mips_bus_space_generic;
sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
return(uart_bus_probe(dev, 0, 0, 0, 0));
return(uart_bus_probe(dev, 0, 0, 0, 0, 0));
}
DRIVER_MODULE(uart, obio, uart_malta_driver, uart_devclass, 0, 0);

2
sys/mips/rmi/uart_bus_xlr_iodi.c
View File

@ -74,7 +74,7 @@ uart_iodi_probe(device_t dev)
sc->sc_bas.bst = rmi_bus_space;
sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(XLR_UART0ADDR);
/* regshft = 2, rclk = 66000000, rid = 0, chan = 0 */
return (uart_bus_probe(dev, 2, 66000000, 0, 0));
return (uart_bus_probe(dev, 2, 0, 66000000, 0, 0));
}
DRIVER_MODULE(uart, iodi, uart_iodi_driver, uart_devclass, 0, 0);

2
sys/mips/rt305x/uart_bus_rt305x.c
View File

@ -87,7 +87,7 @@ uart_rt305x_probe(device_t dev)
sc->sc_bas.bsh =
MIPS_PHYS_TO_KSEG1(device_get_unit(dev)?UARTLITE_BASE:UART_BASE);
return (uart_bus_probe(dev, 2, SYSTEM_CLOCK, 0, 0));
return (uart_bus_probe(dev, 2, 0, SYSTEM_CLOCK, 0, 0));
}
DRIVER_MODULE(uart, obio, uart_rt305x_driver, uart_devclass, 0, 0);

2
sys/powerpc/psim/uart_iobus.c
View File

@ -81,7 +81,7 @@ uart_iobus_probe(device_t dev)
sc->sc_class = &uart_ns8250_class;
device_set_desc(dev, "PSIM serial port");
return (uart_bus_probe(dev, 0, 0, 0, 0));
return (uart_bus_probe(dev, 0, 0, 0, 0, 0));
}
DRIVER_MODULE(uart, iobus, uart_iobus_driver, uart_devclass, 0, 0);

2
sys/sparc64/pci/sbbc.c
View File

@ -618,7 +618,7 @@ sbbc_uart_sbbc_probe(device_t dev)
sc = device_get_softc(dev);
sc->sc_class = &uart_sbbc_class;
device_set_desc(dev, "Serengeti console");
return (uart_bus_probe(dev, 0, 0, SBBC_PCI_BAR, 0));
return (uart_bus_probe(dev, 0, 0, 0, SBBC_PCI_BAR, 0));
}
/*