This commit is contained in:
attilio 2011-05-18 16:01:29 +00:00
parent 0828d417d4
commit 6a2b7fdc52
17 changed files with 121 additions and 106 deletions

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@ -132,6 +132,7 @@ procstat_close(struct procstat *procstat)
assert(procstat);
if (procstat->type == PROCSTAT_KVM)
kvm_close(procstat->kd);
free(procstat);
}
struct procstat *

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@ -216,6 +216,14 @@ printcpuinfo(void)
printf(" Family = %x", CPUID_TO_FAMILY(cpu_id));
printf(" Model = %x", CPUID_TO_MODEL(cpu_id));
printf(" Stepping = %u", cpu_id & CPUID_STEPPING);
/*
* AMD CPUID Specification
* http://support.amd.com/us/Embedded_TechDocs/25481.pdf
*
* Intel Processor Identification and CPUID Instruction
* http://www.intel.com/assets/pdf/appnote/241618.pdf
*/
if (cpu_high > 0) {
/*
@ -277,38 +285,29 @@ printcpuinfo(void)
"\012SSSE3" /* SSSE3 */
"\013CNXT-ID" /* L1 context ID available */
"\014<b11>"
"\015<b12>"
"\015FMA" /* Fused Multiply Add */
"\016CX16" /* CMPXCHG16B Instruction */
"\017xTPR" /* Send Task Priority Messages*/
"\020PDCM" /* Perf/Debug Capability MSR */
"\021<b16>"
"\022PCID" /* Process-context Identifiers */
"\022PCID" /* Process-context Identifiers*/
"\023DCA" /* Direct Cache Access */
"\024SSE4.1"
"\025SSE4.2"
"\024SSE4.1" /* SSE 4.1 */
"\025SSE4.2" /* SSE 4.2 */
"\026x2APIC" /* xAPIC Extensions */
"\027MOVBE"
"\030POPCNT"
"\031<b24>"
"\032AESNI" /* AES Crypto*/
"\033XSAVE"
"\034OSXSAVE"
"\035<b28>"
"\036<b29>"
"\027MOVBE" /* MOVBE Instruction */
"\030POPCNT" /* POPCNT Instruction */
"\031TSCDLT" /* TSC-Deadline Timer */
"\032AESNI" /* AES Crypto */
"\033XSAVE" /* XSAVE/XRSTOR States */
"\034OSXSAVE" /* OS-Enabled State Management*/
"\035AVX" /* Advanced Vector Extensions */
"\036F16C" /* Half-precision conversions */
"\037<b30>"
"\040HV" /* Hypervisor */
);
}
/*
* AMD64 Architecture Programmer's Manual Volume 3:
* General-Purpose and System Instructions
* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
*
* IA-32 Intel Architecture Software Developer's Manual,
* Volume 2A: Instruction Set Reference, A-M
* ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
*/
if (amd_feature != 0) {
printf("\n AMD Features=0x%b", amd_feature,
"\020" /* in hex */
@ -361,18 +360,18 @@ printcpuinfo(void)
"\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
"\012OSVW" /* OS visible workaround */
"\013IBS" /* Instruction based sampling */
"\014SSE5" /* SSE5 */
"\014XOP" /* XOP extended instructions */
"\015SKINIT" /* SKINIT/STGI */
"\016WDT" /* Watchdog timer */
"\017<b14>"
"\020<b15>"
"\021<b16>"
"\020LWP" /* Lightweight Profiling */
"\021FMA4" /* 4-operand FMA instructions */
"\022<b17>"
"\023<b18>"
"\024<b19>"
"\024NodeId" /* NodeId MSR support */
"\025<b20>"
"\026<b21>"
"\027<b22>"
"\026TBM" /* Trailing Bit Manipulation */
"\027Topology" /* Topology Extensions */
"\030<b23>"
"\031<b24>"
"\032<b25>"

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@ -123,6 +123,7 @@
#define CPUID2_TM2 0x00000100
#define CPUID2_SSSE3 0x00000200
#define CPUID2_CNXTID 0x00000400
#define CPUID2_FMA 0x00001000
#define CPUID2_CX16 0x00002000
#define CPUID2_XTPR 0x00004000
#define CPUID2_PDCM 0x00008000
@ -133,7 +134,12 @@
#define CPUID2_X2APIC 0x00200000
#define CPUID2_MOVBE 0x00400000
#define CPUID2_POPCNT 0x00800000
#define CPUID2_TSCDLT 0x01000000
#define CPUID2_AESNI 0x02000000
#define CPUID2_XSAVE 0x04000000
#define CPUID2_OSXSAVE 0x08000000
#define CPUID2_AVX 0x10000000
#define CPUID2_F16C 0x20000000
#define CPUID2_HV 0x80000000
/*
@ -170,9 +176,14 @@
#define AMDID2_PREFETCH 0x00000100
#define AMDID2_OSVW 0x00000200
#define AMDID2_IBS 0x00000400
#define AMDID2_SSE5 0x00000800
#define AMDID2_XOP 0x00000800
#define AMDID2_SKINIT 0x00001000
#define AMDID2_WDT 0x00002000
#define AMDID2_LWP 0x00008000
#define AMDID2_FMA4 0x00010000
#define AMDID2_NODE_ID 0x00080000
#define AMDID2_TBM 0x00200000
#define AMDID2_TOPOLOGY 0x00400000
/*
* CPUID instruction 1 eax info

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@ -689,6 +689,9 @@ zfs_secpolicy_destroy(zfs_cmd_t *zc, cred_t *cr)
* and destroying snapshots requires descendent permissions, a successfull
* check of the top level snapshot applies to snapshots of all descendent
* datasets as well.
*
* The top level snapshot may not exist when doing a recursive destroy.
* In this case fallback to permissions of the parent dataset.
*/
static int
zfs_secpolicy_destroy_snaps(zfs_cmd_t *zc, cred_t *cr)
@ -700,6 +703,9 @@ zfs_secpolicy_destroy_snaps(zfs_cmd_t *zc, cred_t *cr)
error = zfs_secpolicy_destroy_perms(dsname, cr);
if (error == ENOENT)
error = zfs_secpolicy_destroy_perms(zc->zc_name, cr);
strfree(dsname);
return (error);
}

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@ -1368,10 +1368,6 @@ ar5416UpdateChainMasks(struct ath_hal *ah, HAL_BOOL is_ht)
AH5416(ah)->ah_rx_chainmask);
}
#ifndef IS_5GHZ_FAST_CLOCK_EN
#define IS_5GHZ_FAST_CLOCK_EN(ah, chan) AH_FALSE
#endif
void
ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
{

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@ -161,9 +161,10 @@ dot11rate_label(const HAL_RATE_TABLE *rt, int rix)
* or -1 if all the average_tx_times are 0.
*/
static __inline int
pick_best_rate(struct sample_node *sn, const HAL_RATE_TABLE *rt,
pick_best_rate(struct ath_node *an, const HAL_RATE_TABLE *rt,
int size_bin, int require_acked_before)
{
struct sample_node *sn = ATH_NODE_SAMPLE(an);
int best_rate_rix, best_rate_tt;
uint32_t mask;
int rix, tt;
@ -174,6 +175,12 @@ pick_best_rate(struct sample_node *sn, const HAL_RATE_TABLE *rt,
if ((mask & 1) == 0) /* not a supported rate */
continue;
/* Don't pick a non-HT rate for a HT node */
if ((an->an_node.ni_flags & IEEE80211_NODE_HT) &&
(rt->info[rix].phy != IEEE80211_T_HT)) {
continue;
}
tt = sn->stats[size_bin][rix].average_tx_time;
if (tt <= 0 ||
(require_acked_before &&
@ -196,11 +203,12 @@ pick_best_rate(struct sample_node *sn, const HAL_RATE_TABLE *rt,
* Pick a good "random" bit-rate to sample other than the current one.
*/
static __inline int
pick_sample_rate(struct sample_softc *ssc , struct sample_node *sn,
pick_sample_rate(struct sample_softc *ssc , struct ath_node *an,
const HAL_RATE_TABLE *rt, int size_bin)
{
#define DOT11RATE(ix) (rt->info[ix].dot11Rate & IEEE80211_RATE_VAL)
#define MCS(ix) (rt->info[ix].dot11Rate | IEEE80211_RATE_MCS)
struct sample_node *sn = ATH_NODE_SAMPLE(an);
int current_rix, rix;
unsigned current_tt;
uint32_t mask;
@ -208,6 +216,7 @@ pick_sample_rate(struct sample_softc *ssc , struct sample_node *sn,
current_rix = sn->current_rix[size_bin];
if (current_rix < 0) {
/* no successes yet, send at the lowest bit-rate */
/* XXX should return MCS0 if HT */
return 0;
}
@ -223,6 +232,13 @@ pick_sample_rate(struct sample_softc *ssc , struct sample_node *sn,
continue;
}
/* if the node is HT and the rate isn't HT, don't bother sample */
if ((an->an_node.ni_flags & IEEE80211_NODE_HT) &&
(rt->info[rix].phy != IEEE80211_T_HT)) {
mask &= ~(1<<rix);
goto nextrate;
}
/* this bit-rate is always worse than the current one */
if (sn->stats[size_bin][rix].perfect_tx_time > current_tt) {
mask &= ~(1<<rix);
@ -236,10 +252,12 @@ pick_sample_rate(struct sample_softc *ssc , struct sample_node *sn,
goto nextrate;
}
/* don't sample more than 2 rates higher for rates > 11M */
if (DOT11RATE(rix) > 2*11 && rix > current_rix + 2) {
mask &= ~(1<<rix);
goto nextrate;
/* Don't sample more than 2 rates higher for rates > 11M for non-HT rates */
if (! (an->an_node.ni_flags & IEEE80211_NODE_HT)) {
if (DOT11RATE(rix) > 2*11 && rix > current_rix + 2) {
mask &= ~(1<<rix);
goto nextrate;
}
}
sn->last_sample_rix[size_bin] = rix;
@ -327,7 +345,7 @@ ath_rate_findrate(struct ath_softc *sc, struct ath_node *an,
/* XXX TODO: this doesn't know about 11gn vs 11g protection; teach it */
mrr = sc->sc_mrretry && !(ic->ic_flags & IEEE80211_F_USEPROT);
best_rix = pick_best_rate(sn, rt, size_bin, !mrr);
best_rix = pick_best_rate(an, rt, size_bin, !mrr);
if (best_rix >= 0) {
average_tx_time = sn->stats[size_bin][best_rix].average_tx_time;
} else {
@ -338,7 +356,7 @@ ath_rate_findrate(struct ath_softc *sc, struct ath_node *an,
* rates to sample_rate% of the total transmission time.
*/
if (sn->sample_tt[size_bin] < average_tx_time * (sn->packets_since_sample[size_bin]*ssc->sample_rate/100)) {
rix = pick_sample_rate(ssc, sn, rt, size_bin);
rix = pick_sample_rate(ssc, an, rt, size_bin);
IEEE80211_NOTE(an->an_node.ni_vap, IEEE80211_MSG_RATECTL,
&an->an_node, "size %u sample rate %d current rate %d",
bin_to_size(size_bin), RATE(rix),

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@ -539,9 +539,6 @@ uaudio_probe(device_t dev)
if (uaa->usb_mode != USB_MODE_HOST)
return (ENXIO);
if (uaa->use_generic == 0)
return (ENXIO);
/* lookup non-standard device */
if (uaa->info.bInterfaceClass != UICLASS_AUDIO) {
@ -555,7 +552,7 @@ uaudio_probe(device_t dev)
if (usb_test_quirk(uaa, UQ_BAD_AUDIO))
return (ENXIO);
else
return (0);
return (BUS_PROBE_GENERIC);
}
/* check for MIDI stream */
@ -564,7 +561,7 @@ uaudio_probe(device_t dev)
if (usb_test_quirk(uaa, UQ_BAD_MIDI))
return (ENXIO);
else
return (0);
return (BUS_PROBE_GENERIC);
}
return (ENXIO);
}

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@ -617,10 +617,6 @@ uhid_probe(device_t dev)
if (uaa->usb_mode != USB_MODE_HOST) {
return (ENXIO);
}
if (uaa->use_generic == 0) {
/* give Mouse and Keyboard drivers a try first */
return (ENXIO);
}
if (uaa->info.bInterfaceClass != UICLASS_HID) {
/* the Xbox 360 gamepad doesn't use the HID class */

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@ -771,7 +771,7 @@ ukbd_probe(device_t dev)
if (usb_test_quirk(uaa, UQ_KBD_IGNORE))
return (ENXIO);
else
return (BUS_PROBE_GENERIC);
return (BUS_PROBE_DEFAULT);
}
error = usbd_req_get_hid_desc(uaa->device, NULL,
@ -793,7 +793,7 @@ ukbd_probe(device_t dev)
if (usb_test_quirk(uaa, UQ_KBD_IGNORE))
error = ENXIO;
else
error = BUS_PROBE_GENERIC;
error = BUS_PROBE_DEFAULT;
} else
error = ENXIO;

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@ -373,7 +373,7 @@ ums_probe(device_t dev)
if ((uaa->info.bInterfaceSubClass == UISUBCLASS_BOOT) &&
(uaa->info.bInterfaceProtocol == UIPROTO_MOUSE))
return (BUS_PROBE_GENERIC);
return (BUS_PROBE_DEFAULT);
error = usbd_req_get_hid_desc(uaa->device, NULL,
&d_ptr, &d_len, M_TEMP, uaa->info.bIfaceIndex);
@ -383,7 +383,7 @@ ums_probe(device_t dev)
if (hid_is_collection(d_ptr, d_len,
HID_USAGE2(HUP_GENERIC_DESKTOP, HUG_MOUSE)))
error = BUS_PROBE_GENERIC;
error = BUS_PROBE_DEFAULT;
else
error = ENXIO;

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@ -782,6 +782,7 @@ umass_probe_proto(device_t dev, struct usb_attach_arg *uaa)
uint32_t proto = umass_get_proto(uaa->iface);
memset(&ret, 0, sizeof(ret));
ret.error = BUS_PROBE_GENERIC;
/* Search for protocol enforcement */
@ -870,10 +871,6 @@ umass_probe(device_t dev)
if (uaa->usb_mode != USB_MODE_HOST) {
return (ENXIO);
}
if (uaa->use_generic == 0) {
/* give other drivers a try first */
return (ENXIO);
}
temp = umass_probe_proto(dev, uaa);
return (temp.error);

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@ -334,10 +334,6 @@ ustorage_fs_probe(device_t dev)
if (uaa->usb_mode != USB_MODE_DEVICE) {
return (ENXIO);
}
if (uaa->use_generic == 0) {
/* give other drivers a try first */
return (ENXIO);
}
/* Check for a standards compliant device */
id = usbd_get_interface_descriptor(uaa->iface);
if ((id == NULL) ||
@ -346,7 +342,7 @@ ustorage_fs_probe(device_t dev)
(id->bInterfaceProtocol != UIPROTO_MASS_BBB)) {
return (ENXIO);
}
return (0);
return (BUS_PROBE_GENERIC);
}
static int

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@ -1334,7 +1334,6 @@ usb_probe_and_attach(struct usb_device *udev, uint8_t iface_index)
uaa.info.bIfaceIndex = i;
uaa.info.bIfaceNum =
iface->idesc->bInterfaceNumber;
uaa.use_generic = 0;
uaa.driver_info = 0; /* reset driver_info */
DPRINTFN(2, "iclass=%u/%u/%u iindex=%u/%u\n",
@ -1344,16 +1343,6 @@ usb_probe_and_attach(struct usb_device *udev, uint8_t iface_index)
uaa.info.bIfaceIndex,
uaa.info.bIfaceNum);
/* try specific interface drivers first */
if (usb_probe_and_attach_sub(udev, &uaa)) {
/* ignore */
}
/* try generic interface drivers last */
uaa.use_generic = 1;
uaa.driver_info = 0; /* reset driver_info */
if (usb_probe_and_attach_sub(udev, &uaa)) {
/* ignore */
}

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@ -357,7 +357,6 @@ struct usb_attach_arg {
struct usb_interface *iface; /* current interface */
enum usb_hc_mode usb_mode; /* host or device mode */
uint8_t port;
uint8_t use_generic; /* hint for generic drivers */
uint8_t dev_state;
#define UAA_DEV_READY 0
#define UAA_DEV_DISABLED 1

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@ -693,6 +693,13 @@ printcpuinfo(void)
printf(" Stepping = %u", cpu_id & CPUID_STEPPING);
if (cpu_vendor_id == CPU_VENDOR_CYRIX)
printf("\n DIR=0x%04x", cyrix_did);
/*
* AMD CPUID Specification
* http://support.amd.com/us/Embedded_TechDocs/25481.pdf
*
* Intel Processor Identification and CPUID Instruction
* http://www.intel.com/assets/pdf/appnote/241618.pdf
*/
if (cpu_high > 0) {
/*
@ -754,38 +761,29 @@ printcpuinfo(void)
"\012SSSE3" /* SSSE3 */
"\013CNXT-ID" /* L1 context ID available */
"\014<b11>"
"\015<b12>"
"\015FMA" /* Fused Multiply Add */
"\016CX16" /* CMPXCHG16B Instruction */
"\017xTPR" /* Send Task Priority Messages*/
"\020PDCM" /* Perf/Debug Capability MSR */
"\021<b16>"
"\022PCID" /* Process-context Identifiers */
"\022PCID" /* Process-context Identifiers*/
"\023DCA" /* Direct Cache Access */
"\024SSE4.1"
"\025SSE4.2"
"\024SSE4.1" /* SSE 4.1 */
"\025SSE4.2" /* SSE 4.2 */
"\026x2APIC" /* xAPIC Extensions */
"\027MOVBE"
"\030POPCNT"
"\031<b24>"
"\032AESNI" /* AES Crypto*/
"\033XSAVE"
"\034OSXSAVE"
"\035<b28>"
"\036<b29>"
"\027MOVBE" /* MOVBE Instruction */
"\030POPCNT" /* POPCNT Instruction */
"\031TSCDLT" /* TSC-Deadline Timer */
"\032AESNI" /* AES Crypto */
"\033XSAVE" /* XSAVE/XRSTOR States */
"\034OSXSAVE" /* OS-Enabled State Management*/
"\035AVX" /* Advanced Vector Extensions */
"\036F16C" /* Half-precision conversions */
"\037<b30>"
"\040HV" /* Hypervisor */
);
}
/*
* AMD64 Architecture Programmer's Manual Volume 3:
* General-Purpose and System Instructions
* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
*
* IA-32 Intel Architecture Software Developer's Manual,
* Volume 2A: Instruction Set Reference, A-M
* ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
*/
if (amd_feature != 0) {
printf("\n AMD Features=0x%b", amd_feature,
"\020" /* in hex */
@ -838,18 +836,18 @@ printcpuinfo(void)
"\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
"\012OSVW" /* OS visible workaround */
"\013IBS" /* Instruction based sampling */
"\014SSE5" /* SSE5 */
"\014XOP" /* XOP extended instructions */
"\015SKINIT" /* SKINIT/STGI */
"\016WDT" /* Watchdog timer */
"\017<b14>"
"\020<b15>"
"\021<b16>"
"\020LWP" /* Lightweight Profiling */
"\021FMA4" /* 4-operand FMA instructions */
"\022<b17>"
"\023<b18>"
"\024<b19>"
"\024NodeId" /* NodeId MSR support */
"\025<b20>"
"\026<b21>"
"\027<b22>"
"\026TBM" /* Trailing Bit Manipulation */
"\027Topology" /* Topology Extensions */
"\030<b23>"
"\031<b24>"
"\032<b25>"

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@ -120,6 +120,7 @@
#define CPUID2_TM2 0x00000100
#define CPUID2_SSSE3 0x00000200
#define CPUID2_CNXTID 0x00000400
#define CPUID2_FMA 0x00001000
#define CPUID2_CX16 0x00002000
#define CPUID2_XTPR 0x00004000
#define CPUID2_PDCM 0x00008000
@ -130,7 +131,12 @@
#define CPUID2_X2APIC 0x00200000
#define CPUID2_MOVBE 0x00400000
#define CPUID2_POPCNT 0x00800000
#define CPUID2_TSCDLT 0x01000000
#define CPUID2_AESNI 0x02000000
#define CPUID2_XSAVE 0x04000000
#define CPUID2_OSXSAVE 0x08000000
#define CPUID2_AVX 0x10000000
#define CPUID2_F16C 0x20000000
#define CPUID2_HV 0x80000000
/*
@ -167,9 +173,14 @@
#define AMDID2_PREFETCH 0x00000100
#define AMDID2_OSVW 0x00000200
#define AMDID2_IBS 0x00000400
#define AMDID2_SSE5 0x00000800
#define AMDID2_XOP 0x00000800
#define AMDID2_SKINIT 0x00001000
#define AMDID2_WDT 0x00002000
#define AMDID2_LWP 0x00008000
#define AMDID2_FMA4 0x00010000
#define AMDID2_NODE_ID 0x00080000
#define AMDID2_TBM 0x00200000
#define AMDID2_TOPOLOGY 0x00400000
/*
* CPUID instruction 1 eax info

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@ -409,6 +409,7 @@ static int
ubt_probe(device_t dev)
{
struct usb_attach_arg *uaa = device_get_ivars(dev);
int error;
if (uaa->usb_mode != USB_MODE_HOST)
return (ENXIO);
@ -416,14 +417,14 @@ ubt_probe(device_t dev)
if (uaa->info.bIfaceIndex != 0)
return (ENXIO);
if (uaa->use_generic == 0)
return (ENXIO);
if (usbd_lookup_id_by_uaa(ubt_ignore_devs,
sizeof(ubt_ignore_devs), uaa) == 0)
return (ENXIO);
return (usbd_lookup_id_by_uaa(ubt_devs, sizeof(ubt_devs), uaa));
error = usbd_lookup_id_by_uaa(ubt_devs, sizeof(ubt_devs), uaa);
if (error == 0)
return (BUS_PROBE_GENERIC);
return (error);
} /* ubt_probe */
/*