Add register definitions for Intel 82437FX (Triton System Controller)
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wollman
parent
ae387d6ba2
commit
6ae0d73e93
@ -1,6 +1,6 @@
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/**************************************************************************
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/**************************************************************************
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**
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**
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** $Id: pcisupport.c,v 1.23 1995/12/05 20:40:10 bde Exp $
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** $Id: pcisupport.c,v 1.24 1995/12/14 09:54:11 phk Exp $
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**
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**
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** Device driver for DEC/INTEL PCI chipsets.
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** Device driver for DEC/INTEL PCI chipsets.
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**
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**
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@ -369,6 +369,97 @@ static const struct condmsg conf82378[] =
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{ 0 }
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{ 0 }
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};
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};
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static const struct condmsg conf82437fx[] =
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{
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/* PCON -- PCI Control Register */
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{ 0x00, 0x00, 0x00, M_TR, "\tCPU Inactivity timer: " },
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{ 0x50, 0xe0, 0xe0, M_EQ, "8" },
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{ 0x50, 0xe0, 0xd0, M_EQ, "7" },
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{ 0x50, 0xe0, 0xc0, M_EQ, "6" },
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{ 0x50, 0xe0, 0xb0, M_EQ, "5" },
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{ 0x50, 0xe0, 0xa0, M_EQ, "4" },
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{ 0x50, 0xe0, 0x90, M_EQ, "3" },
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{ 0x50, 0xe0, 0x80, M_EQ, "2" },
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{ 0x50, 0xe0, 0x00, M_EQ, "1" },
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{ 0x00, 0x00, 0x00, M_TR, " clocks\n\tPeer Concurrency: " },
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{ 0x50, 0x08, 0x08, M_EQ, "enabled" },
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{ 0x50, 0x08, 0x00, M_EQ, "disabled" },
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{ 0x00, 0x00, 0x00, M_TR, "\n\tCPU-to-PCI Write Busting: " },
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{ 0x50, 0x04, 0x00, M_EQ, "enabled" },
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{ 0x50, 0x04, 0x04, M_EQ, "disabled" },
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{ 0x00, 0x00, 0x00, M_TR, "\n\tPCI Streaming: " },
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{ 0x50, 0x02, 0x00, M_EQ, "enabled" },
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{ 0x50, 0x02, 0x02, M_EQ, "disabled" },
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{ 0x00, 0x00, 0x00, M_TR, "\n\tBus Concurrency: " },
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{ 0x50, 0x01, 0x00, M_EQ, "enabled\n" },
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{ 0x50, 0x01, 0x01, M_EQ, "disabled\n" },
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/* CC -- Cache Control Regsiter */
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{ 0x00, 0x00, 0x00, M_TR, "\tCache:" },
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{ 0x52, 0xc0, 0x80, M_EQ, " 512K" },
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{ 0x52, 0xc0, 0x40, M_EQ, " 256K" },
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{ 0x52, 0xc0, 0x00, M_EQ, " NO" },
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{ 0x52, 0x30, 0x00, M_EQ, " pipelined-burst" },
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{ 0x52, 0x30, 0x10, M_EQ, " burst" },
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{ 0x52, 0x30, 0x20, M_EQ, " asynchronous" },
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{ 0x52, 0x30, 0x30, M_EQ, " dual-bank pipelined-burst" },
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{ 0x00, 0x00, 0x00, M_TR, " secondary; L1 " },
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{ 0x52, 0x01, 0x01, M_EQ, "disabled" },
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{ 0x52, 0x01, 0x00, M_EQ, "enabled" },
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{ 0x00, 0x00, 0x00, M_TR, "\n" },
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/* DRAMC -- DRAM Control Register */
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{ 0x57, 0x07, 0x00, M_EQ, "Warning: refresh OFF!\n" },
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{ 0x00, 0x00, 0x00, M_TR, "\tDRAM:" },
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{ 0x57, 0xc0, 0x00, M_EQ, " no memory hole" },
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{ 0x57, 0xc0, 0x40, M_EQ, " 512K-640K memory hole" },
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{ 0x57, 0xc0, 0x80, M_EQ, " 15M-16M memory hole" },
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{ 0x57, 0x07, 0x01, M_EQ, ", 50 MHz refresh" },
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{ 0x57, 0x07, 0x02, M_EQ, ", 60 MHz refresh" },
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{ 0x57, 0x07, 0x03, M_EQ, ", 66 MHz refresh" },
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/* DRAMT = DRAM Timing Register */
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{ 0x00, 0x00, 0x00, M_TR, "\n\tRead burst timing: " },
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{ 0x58, 0x60, 0x00, M_EQ, "x-4-4-4/x-4-4-4" },
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{ 0x58, 0x60, 0x20, M_EQ, "x-3-3-3/x-4-4-4" },
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{ 0x58, 0x60, 0x40, M_EQ, "x-2-2-2/x-3-3-3" },
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{ 0x58, 0x60, 0x60, M_EQ, "???" },
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{ 0x00, 0x00, 0x00, M_TR, "\n\tWrite burst timing: " },
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{ 0x58, 0x18, 0x00, M_EQ, "x-4-4-4" },
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{ 0x58, 0x18, 0x08, M_EQ, "x-3-3-3" },
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{ 0x58, 0x18, 0x10, M_EQ, "x-2-2-2" },
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{ 0x58, 0x18, 0x18, M_EQ, "???" },
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{ 0x00, 0x00, 0x00, M_TR, "\n\tRAS-CAS delay: " },
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{ 0x58, 0x04, 0x00, M_EQ, "3" },
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{ 0x58, 0x04, 0x04, M_EQ, "2" },
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{ 0x00, 0x00, 0x00, M_TR, " clocks\n" },
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#ifdef notdef /* XXX not very useful... */
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#define B(x) (1 << x)
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/* PAMs -- Programmable Attribute Map Registers */
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{ 0x00, 0x00, 0x00, M_TR, "\tNon-cacheable regions:" },
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{ 0x00, 0x00, 0x00, M_TR, " A0000-BFFFF" },
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{ 0x5a, B(2), 0, M_EQ, " C0000" },
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{ 0x5a, B(6), 0, M_EQ, " C4000" },
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{ 0x5b, B(2), 0, M_EQ, " C8000" },
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{ 0x5b, B(6), 0, M_EQ, " CC000" },
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{ 0x5c, B(2), 0, M_EQ, " D0000" },
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{ 0x5c, B(6), 0, M_EQ, " D4000" },
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{ 0x5d, B(2), 0, M_EQ, " D8000" },
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{ 0x5d, B(6), 0, M_EQ, " DC000" },
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{ 0x5e, B(2), 0, M_EQ, " E0000" },
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{ 0x5e, B(6), 0, M_EQ, " E4000" },
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{ 0x5f, B(2), 0, M_EQ, " E8000" },
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{ 0x5f, B(6), 0, M_EQ, " EC000" },
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{ 0x59, B(6), 0, M_EQ, " F0000" },
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/* don't bother with r-o, w-o, r-w, disabled */
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#endif
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/* end marker */
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{ 0 }
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};
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static char confread (pcici_t config_id, int port)
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static char confread (pcici_t config_id, int port)
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{
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{
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unsigned long portw = port & ~3;
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unsigned long portw = port & ~3;
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@ -430,6 +521,9 @@ chipset_attach (pcici_t config_id, int unit)
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pci_conf_read (config_id, 0x50),
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pci_conf_read (config_id, 0x50),
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pci_conf_read (config_id, 0x54));
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pci_conf_read (config_id, 0x54));
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break;
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break;
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case 0x122d8086:
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writeconfig (config_id, conf82437fx);
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break;
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};
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};
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#endif /* PCI_QUIET */
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#endif /* PCI_QUIET */
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}
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}
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