Don't check and warn about pmap mismatch on every call to busdma sync.

With some recent busdma refactoring, sometimes it happens that a sync
op gets called when bus_dmamap_load() never got called, which results
in a spurious warning about a map mismatch when no sync operations will
actually happen anyway.  Now the check is done only if a sync operation
is actually performed, and the result of the check is a panic, not just
a printf.

Reviewed by:	cognet (who prevented me from donning a point hat)
This commit is contained in:
ian 2013-03-23 17:17:06 +00:00
parent 440f1aaedb
commit 6b18376e62

View File

@ -1150,19 +1150,16 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op)
vm_offset_t bbuf;
char _tmp_cl[arm_dcache_align], _tmp_clend[arm_dcache_align];
#endif
/* if buffer was from user space, it it possible that this
* is not the same vm map. The fix is to map each page in
* the buffer into the current address space (KVM) and then
* do the bounce copy or sync list cache operation.
*
* The sync list entries are already broken into
* their respective physical pages.
*/
if (!pmap_dmap_iscurrent(map->pmap))
printf("_bus_dmamap_sync: wrong user map: %p %x\n", map->pmap, op);
/*
* If the buffer was from user space, it is possible that this is not
* the same vm map, especially on a POST operation. It's not clear that
* dma on userland buffers can work at all right now, certainly not if a
* partial cacheline flush has to be handled. To be safe, until we're
* able to test direct userland dma, panic on a map mismatch.
*/
if ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) {
if (!pmap_dmap_iscurrent(map->pmap))
panic("_bus_dmamap_sync: wrong user map for bounce sync.");
/* Handle data bouncing. */
CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x "
"performing bounce", __func__, dmat, dmat->flags, op);
@ -1188,9 +1185,6 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op)
}
if (op & BUS_DMASYNC_POSTREAD) {
if (!pmap_dmap_iscurrent(map->pmap))
panic("_bus_dmamap_sync: wrong user map. apply fix");
cpu_dcache_inv_range((vm_offset_t)bpage->vaddr,
bpage->datacount);
l2cache_inv_range((vm_offset_t)bpage->vaddr,
@ -1230,6 +1224,8 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op)
return;
if (map->sync_count != 0) {
if (!pmap_dmap_iscurrent(map->pmap))
panic("_bus_dmamap_sync: wrong user map for sync.");
/* ARM caches are not self-snooping for dma */
sl = &map->slist[0];
@ -1303,8 +1299,6 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op)
#ifdef FIX_DMAP_BUS_DMASYNC_POSTREAD
case BUS_DMASYNC_POSTREAD:
if (!pmap_dmap_iscurrent(map->pmap))
panic("_bus_dmamap_sync: wrong user map. apply fix");
while (sl != end) {
/* write back the unaligned portions */
vm_paddr_t physaddr;