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Print the correct bitmask for the running Book-E CPU

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All the Book-E world is no longer e500v{1,2}.  e500mc the 64-bit derivatives do
not use the DOZE/NAP bits with MSR[WE], instead using the `wait' instruction to
wait for interrupts, and SoC plane controls (via CCSR) for power management.

MFC after:	1 week
This commit is contained in:
Justin Hibbits 2017-09-17 19:40:17 +00:00
parent 40427cca7a
commit 6b7530563b
1 changed files with 21 additions and 5 deletions
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26
sys/powerpc/powerpc/cpu.c
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@ -530,16 +530,32 @@ cpu_booke_setup(int cpuid, uint16_t vers)
{
#ifdef BOOKE_E500
register_t hid0;
const char *bitmask;
hid0 = mfspr(SPR_HID0);
/* Programe power-management mode. */
hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
hid0 |= HID0_DOZE;
switch (vers) {
case FSL_E500mc:
bitmask = HID0_E500MC_BITMASK;
break;
case FSL_E5500:
case FSL_E6500:
bitmask = HID0_E5500_BITMASK;
break;
case FSL_E500v1:
case FSL_E500v2:
/* Only e500v1/v2 support HID0 power management setup. */
mtspr(SPR_HID0, hid0);
/* Programe power-management mode. */
hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
hid0 |= HID0_DOZE;
printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, HID0_E500_BITMASK);
mtspr(SPR_HID0, hid0);
default:
bitmask = HID0_E500_BITMASK;
break;
}
printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask);
#endif
if (cpu_idle_hook == NULL)