MFC r259744, cleanups to move global vars into softc, use named values, etc.
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20d3a75430
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6c09b7134e
@ -99,13 +99,16 @@ struct am335x_dmtimer_softc {
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struct resource * tmr_mem_res[AM335X_NUM_TIMERS];
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struct resource * tmr_irq_res[AM335X_NUM_TIMERS];
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uint32_t sysclk_freq;
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struct am335x_dmtimer {
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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struct eventtimer et;
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} t[AM335X_NUM_TIMERS];
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uint32_t tc_num; /* Which timer number is tc. */
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uint32_t et_num; /* Which timer number is et. */
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struct resource * tc_memres; /* Resources for tc timer. */
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struct resource * et_memres; /* Resources for et timer. */
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struct timecounter tc;
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struct eventtimer et;
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};
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static struct am335x_dmtimer_softc *am335x_dmtimer_sc;
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static struct resource_spec am335x_dmtimer_mem_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_MEMORY, 1, RF_ACTIVE },
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@ -129,51 +132,58 @@ static struct resource_spec am335x_dmtimer_irq_spec[] = {
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{ -1, 0, 0 }
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};
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static struct am335x_dmtimer *am335x_dmtimer_tc_tmr = NULL;
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static inline uint32_t
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am335x_dmtimer_tc_read_4(struct am335x_dmtimer_softc *sc, uint32_t reg)
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{
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/* Read/Write macros for Timer used as timecounter */
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#define am335x_dmtimer_tc_read_4(reg) \
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bus_space_read_4(am335x_dmtimer_tc_tmr->bst, \
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am335x_dmtimer_tc_tmr->bsh, reg)
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return (bus_read_4(sc->tc_memres, reg));
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}
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#define am335x_dmtimer_tc_write_4(reg, val) \
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bus_space_write_4(am335x_dmtimer_tc_tmr->bst, \
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am335x_dmtimer_tc_tmr->bsh, reg, val)
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static inline void
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am335x_dmtimer_tc_write_4(struct am335x_dmtimer_softc *sc, uint32_t reg,
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uint32_t val)
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{
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/* Read/Write macros for Timer used as eventtimer */
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#define am335x_dmtimer_et_read_4(reg) \
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bus_space_read_4(tmr->bst, tmr->bsh, reg)
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bus_write_4(sc->tc_memres, reg, val);
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}
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#define am335x_dmtimer_et_write_4(reg, val) \
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bus_space_write_4(tmr->bst, tmr->bsh, reg, val)
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static inline uint32_t
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am335x_dmtimer_et_read_4(struct am335x_dmtimer_softc *sc, uint32_t reg)
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{
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static unsigned am335x_dmtimer_tc_get_timecount(struct timecounter *);
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return (bus_read_4(sc->et_memres, reg));
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}
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static struct timecounter am335x_dmtimer_tc = {
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.tc_name = "AM335x Timecounter",
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.tc_get_timecount = am335x_dmtimer_tc_get_timecount,
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.tc_poll_pps = NULL,
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.tc_counter_mask = ~0u,
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.tc_frequency = 0,
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.tc_quality = 1000,
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};
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static inline void
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am335x_dmtimer_et_write_4(struct am335x_dmtimer_softc *sc, uint32_t reg,
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uint32_t val)
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{
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bus_write_4(sc->et_memres, reg, val);
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}
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static unsigned
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am335x_dmtimer_tc_get_timecount(struct timecounter *tc)
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{
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return am335x_dmtimer_tc_read_4(DMT_TCRR);
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struct am335x_dmtimer_softc *sc;
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sc = tc->tc_priv;
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return (am335x_dmtimer_tc_read_4(sc, DMT_TCRR));
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}
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static int
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am335x_dmtimer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
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{
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struct am335x_dmtimer *tmr = (struct am335x_dmtimer *)et->et_priv;
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uint32_t load, count;
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uint32_t tclr = 0;
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struct am335x_dmtimer_softc *sc;
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uint32_t count, load, tclr;
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sc = et->et_priv;
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tclr = 0;
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if (period != 0) {
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load = ((uint32_t)et->et_frequency * period) >> 32;
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tclr |= 2; /* autoreload bit */
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tclr |= DMT_TCLR_AUTOLOAD;
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panic("periodic timer not implemented\n");
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} else {
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load = 0;
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@ -185,23 +195,24 @@ am335x_dmtimer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
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count = load;
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/* Reset Timer */
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am335x_dmtimer_et_write_4(DMT_TSICR, 2);
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am335x_dmtimer_et_write_4(sc, DMT_TSICR, DMT_TSICR_RESET);
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/* Wait for reset to complete */
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while (am335x_dmtimer_et_read_4(DMT_TIOCP_CFG) & 1);
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while (am335x_dmtimer_et_read_4(sc, DMT_TIOCP_CFG) & DMT_TIOCP_RESET)
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continue;
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/* set load value */
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am335x_dmtimer_et_write_4(DMT_TLDR, 0xFFFFFFFE - load);
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am335x_dmtimer_et_write_4(sc, DMT_TLDR, 0xFFFFFFFE - load);
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/* set counter value */
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am335x_dmtimer_et_write_4(DMT_TCRR, 0xFFFFFFFE - count);
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am335x_dmtimer_et_write_4(sc, DMT_TCRR, 0xFFFFFFFE - count);
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/* enable overflow interrupt */
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am335x_dmtimer_et_write_4(DMT_IRQENABLE_SET, 2);
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am335x_dmtimer_et_write_4(sc, DMT_IRQENABLE_SET, DMT_IRQ_OVF);
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/* start timer(ST) */
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tclr |= 1;
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am335x_dmtimer_et_write_4(DMT_TCLR, tclr);
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tclr |= DMT_TCLR_START;
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am335x_dmtimer_et_write_4(sc, DMT_TCLR, tclr);
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return (0);
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}
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@ -209,13 +220,15 @@ am335x_dmtimer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
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static int
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am335x_dmtimer_stop(struct eventtimer *et)
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{
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struct am335x_dmtimer *tmr = (struct am335x_dmtimer *)et->et_priv;
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struct am335x_dmtimer_softc *sc;
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sc = et->et_priv;
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/* Disable all interrupts */
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am335x_dmtimer_et_write_4(DMT_IRQENABLE_CLR, 7);
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am335x_dmtimer_et_write_4(sc, DMT_IRQENABLE_CLR, DMT_IRQ_MASK);
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/* Stop Timer */
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am335x_dmtimer_et_write_4(DMT_TCLR, 0);
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am335x_dmtimer_et_write_4(sc, DMT_TCLR, 0);
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return (0);
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}
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@ -223,12 +236,13 @@ am335x_dmtimer_stop(struct eventtimer *et)
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static int
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am335x_dmtimer_intr(void *arg)
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{
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struct am335x_dmtimer *tmr = (struct am335x_dmtimer *)arg;
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struct am335x_dmtimer_softc *sc;
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sc = arg;
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/* Ack interrupt */
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am335x_dmtimer_et_write_4(DMT_IRQSTATUS, 7);
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if (tmr->et.et_active)
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tmr->et.et_event_cb(&tmr->et, tmr->et.et_arg);
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am335x_dmtimer_et_write_4(sc, DMT_IRQSTATUS, DMT_IRQ_OVF);
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if (sc->et.et_active)
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sc->et.et_event_cb(&sc->et, sc->et.et_arg);
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return (FILTER_HANDLED);
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}
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@ -236,8 +250,6 @@ am335x_dmtimer_intr(void *arg)
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static int
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am335x_dmtimer_probe(device_t dev)
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{
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struct am335x_dmtimer_softc *sc;
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sc = (struct am335x_dmtimer_softc *)device_get_softc(dev);
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if (ofw_bus_is_compatible(dev, "ti,am335x-dmtimer")) {
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device_set_desc(dev, "AM335x DMTimer");
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@ -250,22 +262,29 @@ am335x_dmtimer_probe(device_t dev)
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static int
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am335x_dmtimer_attach(device_t dev)
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{
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struct am335x_dmtimer_softc *sc = device_get_softc(dev);
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struct am335x_dmtimer_softc *sc;
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void *ihl;
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int err;
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int i;
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if (am335x_dmtimer_tc_tmr != NULL)
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/*
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* Note that if this routine returns an error status rather than running
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* to completion it makes no attempt to clean up allocated resources;
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* the system is essentially dead anyway without functional timers.
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*/
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sc = device_get_softc(dev);
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if (am335x_dmtimer_sc != NULL)
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return (EINVAL);
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/* Get the base clock frequency */
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/* Get the base clock frequency. */
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err = ti_prcm_clk_get_source_freq(SYS_CLK, &sc->sysclk_freq);
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if (err) {
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device_printf(dev, "Error: could not get sysclk frequency\n");
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return (ENXIO);
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}
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/* Request the memory resources */
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/* Request the memory resources. */
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err = bus_alloc_resources(dev, am335x_dmtimer_mem_spec,
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sc->tmr_mem_res);
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if (err) {
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@ -273,7 +292,7 @@ am335x_dmtimer_attach(device_t dev)
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return (ENXIO);
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}
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/* Request the IRQ resources */
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/* Request the IRQ resources. */
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err = bus_alloc_resources(dev, am335x_dmtimer_irq_spec,
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sc->tmr_irq_res);
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if (err) {
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@ -281,65 +300,64 @@ am335x_dmtimer_attach(device_t dev)
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return (ENXIO);
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}
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for(i=0;i<AM335X_NUM_TIMERS;i++) {
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sc->t[i].bst = rman_get_bustag(sc->tmr_mem_res[i]);
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sc->t[i].bsh = rman_get_bushandle(sc->tmr_mem_res[i]);
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}
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/* Configure DMTimer3 as eventtimer and DMTimer4 as timecounter. */
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sc->et_num = 3;
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sc->tc_num = 2;
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sc->et_memres = sc->tmr_mem_res[sc->et_num];
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sc->tc_memres = sc->tmr_mem_res[sc->tc_num];
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/* Configure DMTimer2 and DMTimer3 source and enable them */
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err = ti_prcm_clk_set_source(DMTIMER2_CLK, SYSCLK_CLK);
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err |= ti_prcm_clk_enable(DMTIMER2_CLK);
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err |= ti_prcm_clk_set_source(DMTIMER3_CLK, SYSCLK_CLK);
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err |= ti_prcm_clk_enable(DMTIMER3_CLK);
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err = ti_prcm_clk_set_source(DMTIMER0_CLK + sc->et_num, SYSCLK_CLK);
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err |= ti_prcm_clk_enable(DMTIMER0_CLK + sc->et_num);
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err |= ti_prcm_clk_set_source(DMTIMER0_CLK + sc->tc_num, SYSCLK_CLK);
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err |= ti_prcm_clk_enable(DMTIMER0_CLK + sc->tc_num);
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if (err) {
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device_printf(dev, "Error: could not setup timer clock\n");
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return (ENXIO);
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}
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/* Take DMTimer2 for TC */
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am335x_dmtimer_tc_tmr = &sc->t[2];
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/* Set up timecounter; register tc. */
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am335x_dmtimer_tc_write_4(sc, DMT_TSICR, DMT_TSICR_RESET);
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while (am335x_dmtimer_tc_read_4(sc, DMT_TIOCP_CFG) & DMT_TIOCP_RESET)
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continue;
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/* Reset Timer */
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am335x_dmtimer_tc_write_4(DMT_TSICR, 2);
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am335x_dmtimer_tc_write_4(sc, DMT_TLDR, 0);
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am335x_dmtimer_tc_write_4(sc, DMT_TCRR, 0);
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am335x_dmtimer_tc_write_4(sc, DMT_TCLR,
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DMT_TCLR_START | DMT_TCLR_AUTOLOAD);
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/* Wait for reset to complete */
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while (am335x_dmtimer_tc_read_4(DMT_TIOCP_CFG) & 1);
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sc->tc.tc_name = "AM335x Timecounter";
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sc->tc.tc_get_timecount = am335x_dmtimer_tc_get_timecount;
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sc->tc.tc_poll_pps = NULL;
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sc->tc.tc_counter_mask = ~0u;
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sc->tc.tc_frequency = sc->sysclk_freq;
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sc->tc.tc_quality = 1000;
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sc->tc.tc_priv = sc;
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tc_init(&sc->tc);
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/* set load value */
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am335x_dmtimer_tc_write_4(DMT_TLDR, 0);
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/* set counter value */
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am335x_dmtimer_tc_write_4(DMT_TCRR, 0);
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/* Set Timer autoreload(AR) and start timer(ST) */
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am335x_dmtimer_tc_write_4(DMT_TCLR, 3);
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am335x_dmtimer_tc.tc_frequency = sc->sysclk_freq;
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tc_init(&am335x_dmtimer_tc);
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/* Register DMTimer3 as ET */
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/* Setup and enable the timer */
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if (bus_setup_intr(dev, sc->tmr_irq_res[3], INTR_TYPE_CLK,
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am335x_dmtimer_intr, NULL, &sc->t[3], &ihl) != 0) {
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/* Setup eventtimer; register et. */
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if (bus_setup_intr(dev, sc->tmr_irq_res[sc->et_num], INTR_TYPE_CLK,
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am335x_dmtimer_intr, NULL, sc, &ihl) != 0) {
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bus_release_resources(dev, am335x_dmtimer_irq_spec,
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sc->tmr_irq_res);
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device_printf(dev, "Unable to setup the clock irq handler.\n");
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return (ENXIO);
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}
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sc->t[3].et.et_name = "AM335x Eventtimer0";
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sc->t[3].et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
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sc->t[3].et.et_quality = 1000;
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sc->t[3].et.et_frequency = sc->sysclk_freq;
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sc->t[3].et.et_min_period =
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(0x00000002LLU << 32) / sc->t[3].et.et_frequency;
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sc->t[3].et.et_max_period =
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(0xfffffffeLLU << 32) / sc->t[3].et.et_frequency;
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sc->t[3].et.et_start = am335x_dmtimer_start;
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sc->t[3].et.et_stop = am335x_dmtimer_stop;
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sc->t[3].et.et_priv = &sc->t[3];
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et_register(&sc->t[3].et);
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sc->et.et_name = "AM335x Eventtimer";
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sc->et.et_flags = ET_FLAGS_ONESHOT;
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sc->et.et_quality = 1000;
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sc->et.et_frequency = sc->sysclk_freq;
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sc->et.et_min_period =
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((0x00000005LLU << 32) / sc->et.et_frequency);
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sc->et.et_max_period =
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(0xfffffffeLLU << 32) / sc->et.et_frequency;
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sc->et.et_start = am335x_dmtimer_start;
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sc->et.et_stop = am335x_dmtimer_stop;
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sc->et.et_priv = sc;
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et_register(&sc->et);
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/* Store a pointer to the softc for use in DELAY(). */
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am335x_dmtimer_sc = sc;
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return (0);
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}
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@ -370,10 +388,13 @@ cpu_initclocks(void)
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void
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DELAY(int usec)
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{
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int32_t counts;
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struct am335x_dmtimer_softc *sc;
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int32_t counts;
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uint32_t first, last;
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if (am335x_dmtimer_tc_tmr == NULL) {
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sc = am335x_dmtimer_sc;
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if (sc == NULL) {
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for (; usec > 0; usec--)
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for (counts = 200; counts > 0; counts--)
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/* Prevent gcc from optimizing out the loop */
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@ -382,13 +403,13 @@ DELAY(int usec)
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}
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/* Get the number of times to count */
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counts = usec * (am335x_dmtimer_tc.tc_frequency / 1000000) + 1;
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counts = (usec + 1) * (sc->sysclk_freq / 1000000);
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first = am335x_dmtimer_tc_read_4(DMT_TCRR);
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first = am335x_dmtimer_tc_read_4(sc, DMT_TCRR);
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while (counts > 0) {
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last = am335x_dmtimer_tc_read_4(DMT_TCRR);
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if (last>first) {
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last = am335x_dmtimer_tc_read_4(sc, DMT_TCRR);
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if (last > first) {
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counts -= (int32_t)(last - first);
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} else {
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counts -= (int32_t)((0xFFFFFFFF - first) + last);
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