Add cache maintenance functions which will be used by startup code to
initially set up the MMU. Some day they may also be useful as part of
suspend/resume handling, when we get better at power management.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz
This commit is contained in:
Ian Lepore
parent
8d59f6c4da
commit
6c1d9637b7
200
sys/arm/arm/cpu_asm-v6.S
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sys/arm/arm/cpu_asm-v6.S
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@ -0,0 +1,200 @@
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/*-
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* Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
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* Copyright 2014 Michal Meloun <meloun@miracle.cz>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <machine/acle-compat.h>
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#include <machine/asm.h>
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#include <machine/asmacros.h>
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#include <machine/armreg.h>
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#include <machine/sysreg.h>
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#if __ARM_ARCH >= 7
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/*
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* Define cache functions used by startup code, which counts on the fact that
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* only r0-r4,r12 (ip) are modified and no stack space is used. This set
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* of function must be called with interrupts disabled and don't follow
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* ARM ABI (cannot be called form C code.
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* Moreover, it works only with caches integrated to CPU (accessible via CP15).
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*/
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/* Invalidate D cache to PoC. (aka all cache levels)*/
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ASENTRY(dcache_inv_poc_all)
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mrc CP15_CLIDR(r0)
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ands r0, r0, #0x07000000
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mov r0, r0, lsr #23 /* Get LoC (naturally aligned) */
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beq 4f
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1: mcr CP15_CSSELR(r0) /* set cache level */
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isb
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mrc CP15_CCSIDR(r0) /* read CCSIDR */
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ubfx r2, r0, #13, #15 /* get num sets - 1 from CCSIDR */
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ubfx r3, r0, #3, #10 /* get num ways - 1 from CCSIDR */
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clz r1, r3 /* number of bits to MSB of way */
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lsl r3, r3, r1 /* shift into position */
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mov ip, #1
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lsl ip, ip, r1 /* ip now contains the way decr */
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ubfx r0, r0, #0, #3 /* get linesize from CCSIDR */
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add r0, r0, #4 /* apply bias */
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lsl r2, r2, r0 /* shift sets by log2(linesize) */
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add r3, r3, r2 /* merge numsets - 1 with numways - 1 */
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sub ip, ip, r2 /* subtract numsets - 1 from way decr */
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mov r1, #1
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lsl r1, r1, r0 /* r1 now contains the set decr */
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mov r2, ip /* r2 now contains set way decr */
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/* r3 = ways/sets, r2 = way decr, r1 = set decr, r0 and ip are free */
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2: mcr CP15_DCISW(r3) /* invalidate line */
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movs r0, r3 /* get current way/set */
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beq 3f /* at 0 means we are done */
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movs r0, r0, lsl #10 /* clear way bits leaving only set bits*/
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subne r3, r3, r1 /* non-zero?, decrement set */
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subeq r3, r3, r2 /* zero?, decrement way and restore set count */
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b 2b
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3:
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mrc CP15_CSSELR(r0) /* get cache level */
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add r0, r0, #2 /* next level */
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mrc CP15_CLIDR(r1)
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ands r1, r1, #0x07000000
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mov r1, r1, lsr #23 /* Get LoC (naturally aligned) */
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cmp r1, r0
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bgt 1b
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4: dsb /* wait for stores to finish */
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mov r0, #0
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mcr CP15_CSSELR(r0)
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isb
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bx lr
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END(dcache_inv_poc_all)
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/* Invalidate D cache to PoU. (aka L1 cache only)*/
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ASENTRY(dcache_inv_pou_all)
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mrc CP15_CLIDR(r0)
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ands r0, r0, #0x07000000
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mov r0, r0, lsr #26 /* Get LoUU (naturally aligned) */
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beq 4f
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1: mcr CP15_CSSELR(r0) /* set cache level */
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isb
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mrc CP15_CCSIDR(r0) /* read CCSIDR */
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ubfx r2, r0, #13, #15 /* get num sets - 1 from CCSIDR */
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ubfx r3, r0, #3, #10 /* get num ways - 1 from CCSIDR */
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clz r1, r3 /* number of bits to MSB of way */
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lsl r3, r3, r1 /* shift into position */
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mov ip, #1
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lsl ip, ip, r1 /* ip now contains the way decr */
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ubfx r0, r0, #0, #3 /* get linesize from CCSIDR */
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add r0, r0, #4 /* apply bias */
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lsl r2, r2, r0 /* shift sets by log2(linesize) */
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add r3, r3, r2 /* merge numsets - 1 with numways - 1 */
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sub ip, ip, r2 /* subtract numsets - 1 from way decr */
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mov r1, #1
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lsl r1, r1, r0 /* r1 now contains the set decr */
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mov r2, ip /* r2 now contains set way decr */
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/* r3 = ways/sets, r2 = way decr, r1 = set decr, r0 and ip are free */
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2: mcr CP15_DCISW(r3) /* clean & invalidate line */
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movs r0, r3 /* get current way/set */
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beq 3f /* at 0 means we are done */
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movs r0, r0, lsl #10 /* clear way bits leaving only set bits*/
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subne r3, r3, r1 /* non-zero?, decrement set */
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subeq r3, r3, r2 /* zero?, decrement way and restore set count */
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b 2b
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3:
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mrc CP15_CSSELR(r0) /* get cache level */
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add r0, r0, #2 /* next level */
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mrc CP15_CLIDR(r1)
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ands r1, r1, #0x07000000
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mov r1, r1, lsr #26 /* Get LoUU (naturally aligned) */
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cmp r1, r0
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bgt 1b
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4: dsb /* wait for stores to finish */
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mov r0, #0
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mcr CP15_CSSELR(r0)
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bx lr
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END(dcache_inv_pou_all)
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/* Write back and Invalidate D cache to PoC. */
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ASENTRY(dcache_wbinv_poc_all)
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mrc CP15_CLIDR(r0)
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ands r0, r0, #0x07000000
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mov r0, r0, lsr #23 /* Get LoC (naturally aligned) */
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beq 4f
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1: mcr CP15_CSSELR(r0) /* set cache level */
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isb
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mrc CP15_CCSIDR(r0) /* read CCSIDR */
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ubfx r2, r0, #13, #15 /* get num sets - 1 from CCSIDR */
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ubfx r3, r0, #3, #10 /* get num ways - 1 from CCSIDR */
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clz r1, r3 /* number of bits to MSB of way */
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lsl r3, r3, r1 /* shift into position */
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mov ip, #1
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lsl ip, ip, r1 /* ip now contains the way decr */
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ubfx r0, r0, #0, #3 /* get linesize from CCSIDR */
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add r0, r0, #4 /* apply bias */
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lsl r2, r2, r0 /* shift sets by log2(linesize) */
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add r3, r3, r2 /* merge numsets - 1 with numways - 1 */
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sub ip, ip, r2 /* subtract numsets - 1 from way decr */
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mov r1, #1
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lsl r1, r1, r0 /* r1 now contains the set decr */
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mov r2, ip /* r2 now contains set way decr */
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/* r3 = ways/sets, r2 = way decr, r1 = set decr, r0 and ip are free */
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2: mcr CP15_DCCISW(r3) /* clean & invalidate line */
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movs r0, r3 /* get current way/set */
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beq 3f /* at 0 means we are done */
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movs r0, r0, lsl #10 /* clear way bits leaving only set bits*/
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subne r3, r3, r1 /* non-zero?, decrement set */
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subeq r3, r3, r2 /* zero?, decrement way and restore set count */
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b 2b
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3:
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mrc CP15_CSSELR(r0) /* get cache level */
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add r0, r0, #2 /* next level */
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mrc CP15_CLIDR(r1)
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ands r1, r1, #0x07000000
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mov r1, r1, lsr #23 /* Get LoC (naturally aligned) */
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cmp r1, r0
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bgt 1b
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4: dsb /* wait for stores to finish */
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mov r0, #0
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mcr CP15_CSSELR(r0)
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bx lr
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END(dcache_wbinv_poc_all)
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#endif /* __ARM_ARCH >= 7 */
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@ -12,6 +12,7 @@ arm/arm/cpufunc.c standard
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arm/arm/cpufunc_asm.S standard
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arm/arm/cpufunc_asm_armv4.S standard
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arm/arm/cpuinfo.c standard
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arm/arm/cpu_asm-v6.S optional armv6
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arm/arm/db_disasm.c optional ddb
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arm/arm/db_interface.c optional ddb
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arm/arm/db_trace.c optional ddb
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