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- Add hw.clflush_disable loader tunable to avoid panic (trap 9) at

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map_invalidate_cache_range() even if CPU is not Intel.
- This tunable can be set to -1 (default), 0 and 1.  -1 is same as
  current behavior, which automatically disable CLFLUSH on Intel CPUs
  without CPUID_SS (should be occured on Xen only).  You can specify 1
  when this panic happened on non-Intel CPUs (such as AMD's).  Because
  disabling CLFLUSH may reduce performance, you can try with setting 0
  on Intel CPUs without SS to use CLFLUSH feature.

Reviewed by:	kib
Reported by:	karl, kuriyama
Related to:	kern/138863
This commit is contained in:
kuriyama 2009-11-09 02:54:16 +00:00
parent 07fe7b9c9c
commit 6c9aae7fc5
2 changed files with 36 additions and 2 deletions
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19
sys/amd64/amd64/initcpu.c
View File

@ -47,6 +47,13 @@ __FBSDID("$FreeBSD$");
static int hw_instruction_sse; static int hw_instruction_sse;
SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
&hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
/*
* -1: automatic (default)
* 0: keep enable CLFLUSH
* 1: force disable CLFLUSH
*/
static int hw_clflush_disable = -1;
TUNABLE_INT("hw.clflush_disable", &hw_clflush_disable);
int cpu; /* Are we 386, 386sx, 486, etc? */ int cpu; /* Are we 386, 386sx, 486, etc? */
u_int cpu_feature; /* Feature flags */ u_int cpu_feature; /* Feature flags */
@ -169,6 +176,16 @@ initializecpu(void)
* XXXKIB: (temporary) hack to work around traps generated when * XXXKIB: (temporary) hack to work around traps generated when
* CLFLUSHing APIC registers window. * CLFLUSHing APIC registers window.
*/ */
if (cpu_vendor_id == CPU_VENDOR_INTEL && !(cpu_feature & CPUID_SS)) TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
if (cpu_vendor_id == CPU_VENDOR_INTEL && !(cpu_feature & CPUID_SS) &&
hw_clflush_disable == -1)
cpu_feature &= ~CPUID_CLFSH; cpu_feature &= ~CPUID_CLFSH;
/*
* Allow to disable CLFLUSH feature manually by
* hw.clflush_disable tunable. This may help Xen guest on some AMD
* CPUs.
*/
if (hw_clflush_disable == 1) {
cpu_feature &= ~CPUID_CLFSH;
}
} }

19
sys/i386/i386/initcpu.c
View File

@ -75,6 +75,13 @@ static void init_mendocino(void);
static int hw_instruction_sse; static int hw_instruction_sse;
SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
&hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
/*
* -1: automatic (default)
* 0: keep enable CLFLUSH
* 1: force disable CLFLUSH
*/
static int hw_clflush_disable = -1;
TUNABLE_INT("hw.clflush_disable", &hw_clflush_disable);
/* Must *NOT* be BSS or locore will bzero these after setting them */ /* Must *NOT* be BSS or locore will bzero these after setting them */
int cpu = 0; /* Are we 386, 386sx, 486, etc? */ int cpu = 0; /* Are we 386, 386sx, 486, etc? */
@ -721,8 +728,18 @@ initializecpu(void)
* XXXKIB: (temporary) hack to work around traps generated when * XXXKIB: (temporary) hack to work around traps generated when
* CLFLUSHing APIC registers window. * CLFLUSHing APIC registers window.
*/ */
if (cpu_vendor_id == CPU_VENDOR_INTEL && !(cpu_feature & CPUID_SS)) TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
if (cpu_vendor_id == CPU_VENDOR_INTEL && !(cpu_feature & CPUID_SS) &&
hw_clflush_disable == -1)
cpu_feature &= ~CPUID_CLFSH; cpu_feature &= ~CPUID_CLFSH;
/*
* Allow to disable CLFLUSH feature manually by
* hw.clflush_disable tunable. This may help Xen guest on some AMD
* CPUs.
*/
if (hw_clflush_disable == 1) {
cpu_feature &= ~CPUID_CLFSH;
}
#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
/* /*