Add Transmeta Crusoe LongRun support.
Submitted by: Tamotsu HATTORI <athlete@kta.att.ne.jp> Reviewed by: arch@ folks MFC after: 1 week
This commit is contained in:
Mitsuru IWASAKI
parent
ac731e6941
commit
6cee406625
@ -3,7 +3,7 @@
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MAN= aic.4 alpm.4 apm.4 ar.4 asc.4 asr.4 \
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cs.4 cx.4 cy.4 \
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dgb.4 el.4 en.4 ep.4 ex.4 fe.4 gsc.4 \
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ie.4 io.4 labpc.4 le.4 linux.4 lnc.4 matcd.4 mcd.4 \
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ie.4 io.4 labpc.4 le.4 linux.4 lnc.4 longrun.4 matcd.4 mcd.4 \
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meteor.4 mse.4 npx.4 \
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pcf.4 perfmon.4 pnp.4 \
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ray.4 rdp.4 sb.4 scd.4 \
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73
share/man/man4/man4.i386/longrun.4
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73
share/man/man4/man4.i386/longrun.4
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@ -0,0 +1,73 @@
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.\" Copyright (c) 2001 Tamotsu HATTORI <athlete@kta.att.ne.jp>
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.\" Copyright (c) 2001 Mitsuru IWASAKI <iwasaki@FreeBSD.org>
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.Dd Jun 30, 2001
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.Dt LONGRUN 4 i386
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.Os
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.Sh NAME
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.Nm longrun
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.Nd Transmeta(TM) Crusoe(TM) LongRun(TM) support
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.Sh SYNOPSIS
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LongRun support is a collection of power saving modes for the
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Transmeta Crusoe chips, similar in scope to Intel's SpeedStep.
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The following
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.Xr sysctl 8
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MIBs control the different CPU modes:
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.Bl -tag -width "hw.crusoe.percentage integer no " -compact
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.It Sy "Name Type Changeable Description
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.It "hw.crusoe.longrun integer yes LongRun mode.
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.Bl -tag -width "0: minimum frequency mode" -compact
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.It "0: minimum frequency mode
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.It "1: power-saving mode
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.It "2: performance mode
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.It "3: maximum frequency mode
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.El
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.It "hw.crusoe.frequency integer no Current frequency (MHz).
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.It "hw.crusoe.voltage integer no Current voltage (mV).
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.It "hw.crusoe.percentage integer no Processing performance (%).
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.El
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.Pp
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.Sh EXAMPLES
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Print the current status:
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.Bd -literal -offset indent
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% sysctl hw.crusoe
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.Ed
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.Pp
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To set LongRun mode to performance oriented variable frequency mode
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(less power savings):
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.Bd -literal -offset indent
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# sysctl -w hw.crusoe.longrun=2
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.Ed
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.Pp
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.Sh AUTHORS
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.An -nosplit
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LongRun support and this manual page were written by
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.An Tamotsu HATTORI Aq athlete@kta.att.ne.jp
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and
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.An Mitsuru IWASAKI Aq iwasaki@FreeBSD.org .
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.Sh HISTORY
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The Transmeta(TM) Crusoe(TM) LongRun(TM) support first appeared in
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.Fx 5.0 .
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@ -2,6 +2,8 @@
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* Copyright (c) 1992 Terrence R. Lambert.
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* Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
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* Copyright (c) 1997 KATO Takenori.
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* Copyright (c) 2001 Tamotsu Hattori.
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* Copyright (c) 2001 Mitsuru IWASAKI.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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@ -77,6 +79,7 @@ static void print_AMD_features(u_int *regs);
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static void print_AMD_info(u_int amd_maxregs);
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static void print_AMD_assoc(int i);
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static void print_transmeta_info(void);
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static void setup_tmx86_longrun(void);
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static void do_cpuid(u_int ax, u_int *p);
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u_int cyrix_did; /* Device ID of Cyrix CPU */
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@ -621,6 +624,11 @@ printcpuinfo(void)
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printf("\n");
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#endif
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if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
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strcmp(cpu_vendor, "TransmetaCPU") == 0) {
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setup_tmx86_longrun();
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}
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if (!bootverbose)
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return;
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@ -1026,6 +1034,189 @@ print_AMD_features(u_int *regs)
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);
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}
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/*
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* Transmeta Crusoe LongRun Support by Tamotsu Hattori.
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*/
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#define MSR_TMx86_LONGRUN 0x80868010
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#define MSR_TMx86_LONGRUN_FLAGS 0x80868011
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#define LONGRUN_MODE_MASK(x) ((x) & 0x000000007f)
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#define LONGRUN_MODE_RESERVED(x) ((x) & 0xffffff80)
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#define LONGRUN_MODE_WRITE(x, y) (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y))
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#define LONGRUN_MODE_MINFREQUENCY 0x00
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#define LONGRUN_MODE_ECONOMY 0x01
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#define LONGRUN_MODE_PERFORMANCE 0x02
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#define LONGRUN_MODE_MAXFREQUENCY 0x03
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#define LONGRUN_MODE_UNKNOWN 0x04
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#define LONGRUN_MODE_MAX 0x04
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union msrinfo {
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u_int64_t msr;
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u_int32_t regs[2];
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};
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u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
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/* MSR low, MSR high, flags bit0 */
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{ 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */
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{ 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */
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{ 0, 100, 1}, /* LONGRUN_MODE_PERFORMANCE */
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{ 100, 100, 1}, /* LONGRUN_MODE_MAXFREQUENCY */
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};
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static u_int
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tmx86_get_longrun_mode(void)
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{
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u_long eflags;
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union msrinfo msrinfo;
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u_int low, high, flags, mode;
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eflags = read_eflags();
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disable_intr();
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msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
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low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
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high = LONGRUN_MODE_MASK(msrinfo.regs[1]);
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flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;
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for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) {
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if (low == longrun_modes[mode][0] &&
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high == longrun_modes[mode][1] &&
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flags == longrun_modes[mode][2]) {
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goto out;
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}
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}
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mode = LONGRUN_MODE_UNKNOWN;
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out:
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write_eflags(eflags);
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return (mode);
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}
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static u_int
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tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
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{
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u_long eflags;
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u_int regs[4];
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eflags = read_eflags();
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disable_intr();
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do_cpuid(0x80860007, regs);
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*frequency = regs[0];
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*voltage = regs[1];
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*percentage = regs[2];
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write_eflags(eflags);
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return (1);
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}
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static u_int
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tmx86_set_longrun_mode(u_int mode)
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{
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u_long eflags;
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union msrinfo msrinfo;
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if (mode >= LONGRUN_MODE_UNKNOWN) {
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return (0);
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}
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eflags = read_eflags();
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disable_intr();
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/* Write LongRun mode values to Model Specific Register. */
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msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
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msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0],
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longrun_modes[mode][0]);
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msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1],
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longrun_modes[mode][1]);
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wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr);
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/* Write LongRun mode flags to Model Specific Register. */
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msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
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msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
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wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
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write_eflags(eflags);
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return (1);
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}
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static u_int crusoe_longrun;
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static u_int crusoe_frequency;
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static u_int crusoe_voltage;
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static u_int crusoe_percentage;
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static struct sysctl_ctx_list crusoe_sysctl_ctx;
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static struct sysctl_oid *crusoe_sysctl_tree;
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static int
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tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS)
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{
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u_int mode;
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int error;
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crusoe_longrun = tmx86_get_longrun_mode();
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mode = crusoe_longrun;
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error = sysctl_handle_int(oidp, &mode, 0, req);
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if (error || !req->newptr) {
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return (error);
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}
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if (mode >= LONGRUN_MODE_UNKNOWN) {
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error = EINVAL;
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return (error);
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}
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if (crusoe_longrun != mode) {
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crusoe_longrun = mode;
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tmx86_set_longrun_mode(crusoe_longrun);
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}
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return (error);
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}
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static int
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tmx86_status_sysctl(SYSCTL_HANDLER_ARGS)
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{
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u_int val;
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int error;
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tmx86_get_longrun_status(&crusoe_frequency,
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&crusoe_voltage, &crusoe_percentage);
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val = *(u_int *)oidp->oid_arg1;
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error = sysctl_handle_int(oidp, &val, 0, req);
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return (error);
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}
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static void
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setup_tmx86_longrun(void)
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{
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static int done = 0;
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if (done)
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return;
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done++;
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sysctl_ctx_init(&crusoe_sysctl_ctx);
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crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx,
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SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
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"crusoe", CTLFLAG_RD, 0,
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"Transmeta Crusoe LongRun support");
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SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
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OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW,
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&crusoe_longrun, 0, tmx86_longrun_sysctl, "I",
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"LongRun mode [0-3]");
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SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
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OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD,
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&crusoe_frequency, 0, tmx86_status_sysctl, "I",
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"Current frequency (MHz)");
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SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
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OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD,
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&crusoe_voltage, 0, tmx86_status_sysctl, "I",
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"Current voltage (mV)");
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SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
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OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD,
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&crusoe_percentage, 0, tmx86_status_sysctl, "I",
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"Processing performance (%)");
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}
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static void
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print_transmeta_info()
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{
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@ -1059,4 +1250,11 @@ print_transmeta_info()
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info[64] = 0;
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printf(" %s\n", info);
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}
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crusoe_longrun = tmx86_get_longrun_mode();
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tmx86_get_longrun_status(&crusoe_frequency,
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&crusoe_voltage, &crusoe_percentage);
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printf(" LongRun mode: %d <%dMHz %dmV %d%%>\n", crusoe_longrun,
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crusoe_frequency, crusoe_voltage, crusoe_percentage);
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}
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@ -2,6 +2,8 @@
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* Copyright (c) 1992 Terrence R. Lambert.
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* Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
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* Copyright (c) 1997 KATO Takenori.
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* Copyright (c) 2001 Tamotsu Hattori.
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* Copyright (c) 2001 Mitsuru IWASAKI.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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@ -77,6 +79,7 @@ static void print_AMD_features(u_int *regs);
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static void print_AMD_info(u_int amd_maxregs);
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static void print_AMD_assoc(int i);
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static void print_transmeta_info(void);
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static void setup_tmx86_longrun(void);
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static void do_cpuid(u_int ax, u_int *p);
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u_int cyrix_did; /* Device ID of Cyrix CPU */
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@ -621,6 +624,11 @@ printcpuinfo(void)
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printf("\n");
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#endif
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if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
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strcmp(cpu_vendor, "TransmetaCPU") == 0) {
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setup_tmx86_longrun();
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}
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if (!bootverbose)
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return;
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@ -1026,6 +1034,189 @@ print_AMD_features(u_int *regs)
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);
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}
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/*
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* Transmeta Crusoe LongRun Support by Tamotsu Hattori.
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*/
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#define MSR_TMx86_LONGRUN 0x80868010
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#define MSR_TMx86_LONGRUN_FLAGS 0x80868011
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#define LONGRUN_MODE_MASK(x) ((x) & 0x000000007f)
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#define LONGRUN_MODE_RESERVED(x) ((x) & 0xffffff80)
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#define LONGRUN_MODE_WRITE(x, y) (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y))
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#define LONGRUN_MODE_MINFREQUENCY 0x00
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#define LONGRUN_MODE_ECONOMY 0x01
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#define LONGRUN_MODE_PERFORMANCE 0x02
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#define LONGRUN_MODE_MAXFREQUENCY 0x03
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#define LONGRUN_MODE_UNKNOWN 0x04
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#define LONGRUN_MODE_MAX 0x04
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union msrinfo {
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u_int64_t msr;
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u_int32_t regs[2];
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};
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u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
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/* MSR low, MSR high, flags bit0 */
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{ 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */
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{ 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */
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{ 0, 100, 1}, /* LONGRUN_MODE_PERFORMANCE */
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{ 100, 100, 1}, /* LONGRUN_MODE_MAXFREQUENCY */
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};
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static u_int
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tmx86_get_longrun_mode(void)
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{
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u_long eflags;
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union msrinfo msrinfo;
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u_int low, high, flags, mode;
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eflags = read_eflags();
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disable_intr();
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msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
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low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
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high = LONGRUN_MODE_MASK(msrinfo.regs[1]);
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flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;
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for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) {
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if (low == longrun_modes[mode][0] &&
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high == longrun_modes[mode][1] &&
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flags == longrun_modes[mode][2]) {
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goto out;
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}
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}
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mode = LONGRUN_MODE_UNKNOWN;
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out:
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write_eflags(eflags);
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return (mode);
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}
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static u_int
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tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
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{
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u_long eflags;
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u_int regs[4];
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eflags = read_eflags();
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disable_intr();
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do_cpuid(0x80860007, regs);
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*frequency = regs[0];
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*voltage = regs[1];
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*percentage = regs[2];
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write_eflags(eflags);
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return (1);
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}
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static u_int
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tmx86_set_longrun_mode(u_int mode)
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{
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u_long eflags;
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union msrinfo msrinfo;
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||||
if (mode >= LONGRUN_MODE_UNKNOWN) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
eflags = read_eflags();
|
||||
disable_intr();
|
||||
|
||||
/* Write LongRun mode values to Model Specific Register. */
|
||||
msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
|
||||
msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0],
|
||||
longrun_modes[mode][0]);
|
||||
msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1],
|
||||
longrun_modes[mode][1]);
|
||||
wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr);
|
||||
|
||||
/* Write LongRun mode flags to Model Specific Register. */
|
||||
msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
|
||||
msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
|
||||
wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
|
||||
|
||||
write_eflags(eflags);
|
||||
return (1);
|
||||
}
|
||||
|
||||
static u_int crusoe_longrun;
|
||||
static u_int crusoe_frequency;
|
||||
static u_int crusoe_voltage;
|
||||
static u_int crusoe_percentage;
|
||||
static struct sysctl_ctx_list crusoe_sysctl_ctx;
|
||||
static struct sysctl_oid *crusoe_sysctl_tree;
|
||||
|
||||
static int
|
||||
tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS)
|
||||
{
|
||||
u_int mode;
|
||||
int error;
|
||||
|
||||
crusoe_longrun = tmx86_get_longrun_mode();
|
||||
mode = crusoe_longrun;
|
||||
error = sysctl_handle_int(oidp, &mode, 0, req);
|
||||
if (error || !req->newptr) {
|
||||
return (error);
|
||||
}
|
||||
if (mode >= LONGRUN_MODE_UNKNOWN) {
|
||||
error = EINVAL;
|
||||
return (error);
|
||||
}
|
||||
if (crusoe_longrun != mode) {
|
||||
crusoe_longrun = mode;
|
||||
tmx86_set_longrun_mode(crusoe_longrun);
|
||||
}
|
||||
|
||||
return (error);
|
||||
}
|
||||
|
||||
static int
|
||||
tmx86_status_sysctl(SYSCTL_HANDLER_ARGS)
|
||||
{
|
||||
u_int val;
|
||||
int error;
|
||||
|
||||
tmx86_get_longrun_status(&crusoe_frequency,
|
||||
&crusoe_voltage, &crusoe_percentage);
|
||||
val = *(u_int *)oidp->oid_arg1;
|
||||
error = sysctl_handle_int(oidp, &val, 0, req);
|
||||
return (error);
|
||||
}
|
||||
|
||||
static void
|
||||
setup_tmx86_longrun(void)
|
||||
{
|
||||
static int done = 0;
|
||||
|
||||
if (done)
|
||||
return;
|
||||
done++;
|
||||
|
||||
sysctl_ctx_init(&crusoe_sysctl_ctx);
|
||||
crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx,
|
||||
SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
|
||||
"crusoe", CTLFLAG_RD, 0,
|
||||
"Transmeta Crusoe LongRun support");
|
||||
SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
|
||||
OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW,
|
||||
&crusoe_longrun, 0, tmx86_longrun_sysctl, "I",
|
||||
"LongRun mode [0-3]");
|
||||
SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
|
||||
OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD,
|
||||
&crusoe_frequency, 0, tmx86_status_sysctl, "I",
|
||||
"Current frequency (MHz)");
|
||||
SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
|
||||
OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD,
|
||||
&crusoe_voltage, 0, tmx86_status_sysctl, "I",
|
||||
"Current voltage (mV)");
|
||||
SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
|
||||
OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD,
|
||||
&crusoe_percentage, 0, tmx86_status_sysctl, "I",
|
||||
"Processing performance (%)");
|
||||
}
|
||||
|
||||
static void
|
||||
print_transmeta_info()
|
||||
{
|
||||
@ -1059,4 +1250,11 @@ print_transmeta_info()
|
||||
info[64] = 0;
|
||||
printf(" %s\n", info);
|
||||
}
|
||||
|
||||
crusoe_longrun = tmx86_get_longrun_mode();
|
||||
tmx86_get_longrun_status(&crusoe_frequency,
|
||||
&crusoe_voltage, &crusoe_percentage);
|
||||
printf(" LongRun mode: %d <%dMHz %dmV %d%%>\n", crusoe_longrun,
|
||||
crusoe_frequency, crusoe_voltage, crusoe_percentage);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user