Add Intel Cougar Point PCH LPC Controller Device IDs
for watchdog support. Also add additional Intel Ibex Peak (5 Series/3400 Series) PCH IDs. MFC after a week
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@ -110,7 +110,53 @@ static struct ichwd_device ichwd_devices[] = {
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{ DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10 },
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{ DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10 },
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{ DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10 },
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{ DEVICEID_PCH, "Intel PCH watchdog timer", 10 },
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{ DEVICEID_PCHM, "Intel PCH watchdog timer", 10 },
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{ DEVICEID_P55, "Intel P55 watchdog timer", 10 },
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{ DEVICEID_PM55, "Intel PM55 watchdog timer", 10 },
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{ DEVICEID_H55, "Intel H55 watchdog timer", 10 },
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{ DEVICEID_QM57, "Intel QM57 watchdog timer", 10 },
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{ DEVICEID_H57, "Intel H57 watchdog timer", 10 },
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{ DEVICEID_HM55, "Intel HM55 watchdog timer", 10 },
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{ DEVICEID_Q57, "Intel Q57 watchdog timer", 10 },
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{ DEVICEID_HM57, "Intel HM57 watchdog timer", 10 },
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{ DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10 },
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{ DEVICEID_QS57, "Intel QS57 watchdog timer", 10 },
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{ DEVICEID_3400, "Intel 3400 watchdog timer", 10 },
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{ DEVICEID_3420, "Intel 3420 watchdog timer", 10 },
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{ DEVICEID_3450, "Intel 3450 watchdog timer", 10 },
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{ DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10 },
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{ DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10 },
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{ 0, NULL, 0 },
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};
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@ -64,6 +64,38 @@ struct ichwd_softc {
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};
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#define VENDORID_INTEL 0x8086
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#define DEVICEID_CPT0 0x1c40
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#define DEVICEID_CPT1 0x1c41
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#define DEVICEID_CPT2 0x1c42
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#define DEVICEID_CPT3 0x1c43
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#define DEVICEID_CPT4 0x1c44
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#define DEVICEID_CPT5 0x1c45
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#define DEVICEID_CPT6 0x1c46
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#define DEVICEID_CPT7 0x1c47
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#define DEVICEID_CPT8 0x1c48
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#define DEVICEID_CPT9 0x1c49
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#define DEVICEID_CPT10 0x1c4a
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#define DEVICEID_CPT11 0x1c4b
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#define DEVICEID_CPT12 0x1c4c
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#define DEVICEID_CPT13 0x1c4d
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#define DEVICEID_CPT14 0x1c4e
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#define DEVICEID_CPT15 0x1c4f
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#define DEVICEID_CPT16 0x1c50
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#define DEVICEID_CPT17 0x1c51
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#define DEVICEID_CPT18 0x1c52
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#define DEVICEID_CPT19 0x1c53
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#define DEVICEID_CPT20 0x1c54
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#define DEVICEID_CPT21 0x1c55
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#define DEVICEID_CPT22 0x1c56
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#define DEVICEID_CPT23 0x1c57
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#define DEVICEID_CPT24 0x1c58
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#define DEVICEID_CPT25 0x1c59
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#define DEVICEID_CPT26 0x1c5a
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#define DEVICEID_CPT27 0x1c5b
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#define DEVICEID_CPT28 0x1c5c
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#define DEVICEID_CPT29 0x1c5d
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#define DEVICEID_CPT30 0x1c5e
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#define DEVICEID_CPT31 0x1c5f
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#define DEVICEID_82801AA 0x2410
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#define DEVICEID_82801AB 0x2420
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#define DEVICEID_82801BA 0x2440
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@ -100,7 +132,21 @@ struct ichwd_softc {
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#define DEVICEID_ICH10D 0x3a1a
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#define DEVICEID_ICH10DO 0x3a14
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#define DEVICEID_ICH10R 0x3a16
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#define DEVICEID_PCH 0x3b00
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#define DEVICEID_PCHM 0x3b01
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#define DEVICEID_P55 0x3b02
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#define DEVICEID_PM55 0x3b03
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#define DEVICEID_H55 0x3b06
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#define DEVICEID_QM57 0x3b07
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#define DEVICEID_H57 0x3b08
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#define DEVICEID_HM55 0x3b09
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#define DEVICEID_Q57 0x3b0a
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#define DEVICEID_HM57 0x3b0b
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#define DEVICEID_PCHMSFF 0x3b0d
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#define DEVICEID_QS57 0x3b0f
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#define DEVICEID_3400 0x3b12
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#define DEVICEID_3420 0x3b14
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#define DEVICEID_3450 0x3b16
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/* ICH LPC Interface Bridge Registers (ICH5 and older) */
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#define ICH_GEN_STA 0xd4
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