Implement mitigation for Spectre version 2 attacks on ARMv7.
Similarly as we already do for arm64, for mitigation is necessary to flush branch predictor when we: - do task switch - receive prefetch abort on non-userspace address The user can disable this mitigation by setting 'machdep.disable_bp_hardening' sysctl variable, or it can check actual system status by reading 'machdep.spectre_v2_safe' The situation is complicated by fact that: - for Cortex-A8, the BPIALL instruction is effectively NOP until the IBE bit in ACTLR is set. - for Cortex-A15, the BPIALL is always NOP. The branch predictor can be only flushed by doing ICIALLU with special bit (Enable invalidates of BTB) set in ACTLR. Since access to the ACTLR register is locked to secure monitor/firmware on most boards, they will also need update of firmware / U-boot. In worst case, when secure monitor is on-chip ROM (e.g. PandaBoard), the board is unfixable. MFC after: 2 weeks Reviewed by: imp, emaste Differential Revision: https://reviews.freebsd.org/D13931
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mmel
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@ -31,6 +31,8 @@ __FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/pcpu.h>
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#include <sys/smp.h>
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#include <sys/sysctl.h>
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#include <machine/cpu.h>
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@ -40,6 +42,9 @@ __FBSDID("$FreeBSD$");
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#if __ARM_ARCH >= 6
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void reinit_mmu(uint32_t ttb, uint32_t aux_clr, uint32_t aux_set);
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int disable_bp_hardening;
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int spectre_v2_safe = 1;
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#endif
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struct cpuinfo cpuinfo =
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@ -255,6 +260,7 @@ cpuinfo_get_actlr_modifier(uint32_t *actlr_mask, uint32_t *actlr_set)
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if (cpuinfo.implementer == CPU_IMPLEMENTER_ARM) {
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switch (cpuinfo.part_number) {
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case CPU_ARCH_CORTEX_A75:
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case CPU_ARCH_CORTEX_A73:
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case CPU_ARCH_CORTEX_A72:
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case CPU_ARCH_CORTEX_A57:
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@ -338,4 +344,197 @@ cpuinfo_reinit_mmu(uint32_t ttb)
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reinit_mmu(ttb, actlr_mask, actlr_set);
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}
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static bool
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modify_actlr(uint32_t clear, uint32_t set)
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{
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uint32_t reg, newreg;
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reg = cp15_actlr_get();
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newreg = reg;
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newreg &= ~clear;
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newreg |= set;
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if (reg == newreg)
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return (true);
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cp15_actlr_set(newreg);
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reg = cp15_actlr_get();
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if (reg == newreg)
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return (true);
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return (false);
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}
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/* Apply/restore BP hardening on current core. */
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static int
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apply_bp_hardening(bool enable, int kind, bool actrl, uint32_t set_mask)
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{
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if (enable) {
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if (actrl && !modify_actlr(0, set_mask))
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return (-1);
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PCPU_SET(bp_harden_kind, kind);
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} else {
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PCPU_SET(bp_harden_kind, PCPU_BP_HARDEN_KIND_NONE);
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if (actrl)
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modify_actlr(~0, PCPU_GET(original_actlr));
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spectre_v2_safe = 0;
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}
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return (0);
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}
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static void
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handle_bp_hardening(bool enable)
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{
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int kind;
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char *kind_str;
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kind = PCPU_BP_HARDEN_KIND_NONE;
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/*
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* Note: Access to ACTRL is locked to secure world on most boards.
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* This means that full BP hardening depends on updated u-boot/firmware
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* or is impossible at all (if secure monitor is in on-chip ROM).
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*/
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if (cpuinfo.implementer == CPU_IMPLEMENTER_ARM) {
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switch (cpuinfo.part_number) {
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case CPU_ARCH_CORTEX_A8:
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/*
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* For Cortex-A8, IBE bit must be set otherwise
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* BPIALL is effectively NOP.
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* Unfortunately, Cortex-A is also affected by
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* ARM erratum 687067 which causes non-working
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* BPIALL if IBE bit is set and 'Instruction L1 System
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* Array Debug Register 0' is not 0.
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* This register is not reset on power-up and is
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* accessible only from secure world, so we cannot do
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* nothing (nor detect) to fix this issue.
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* I afraid that on chip ROM based secure monitor on
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* AM335x (BeagleBone) doesn't reset this debug
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* register.
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*/
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kind = PCPU_BP_HARDEN_KIND_BPIALL;
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if (apply_bp_hardening(enable, kind, true, 1 << 6) != 0)
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goto actlr_err;
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break;
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break;
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case CPU_ARCH_CORTEX_A9:
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case CPU_ARCH_CORTEX_A12:
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case CPU_ARCH_CORTEX_A17:
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case CPU_ARCH_CORTEX_A57:
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case CPU_ARCH_CORTEX_A72:
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case CPU_ARCH_CORTEX_A73:
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case CPU_ARCH_CORTEX_A75:
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kind = PCPU_BP_HARDEN_KIND_BPIALL;
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if (apply_bp_hardening(enable, kind, false, 0) != 0)
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goto actlr_err;
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break;
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case CPU_ARCH_CORTEX_A15:
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/*
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* For Cortex-A15, set 'Enable invalidates of BTB' bit.
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* Despite this, the BPIALL is still effectively NOP,
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* but with this bit set, the ICIALLU also flushes
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* branch predictor as side effect.
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*/
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kind = PCPU_BP_HARDEN_KIND_ICIALLU;
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if (apply_bp_hardening(enable, kind, true, 1 << 0) != 0)
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goto actlr_err;
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break;
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default:
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break;
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}
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} else if (cpuinfo.implementer == CPU_IMPLEMENTER_QCOM) {
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printf("!!!WARNING!!! CPU(%d) is vulnerable to speculative "
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"branch attacks. !!!\n"
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"Qualcomm Krait cores are known (or believed) to be "
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"vulnerable to \n"
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"speculative branch attacks, no mitigation exists yet.\n",
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PCPU_GET(cpuid));
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goto unkonown_mitigation;
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} else {
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goto unkonown_mitigation;
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}
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if (bootverbose) {
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switch (kind) {
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case PCPU_BP_HARDEN_KIND_NONE:
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kind_str = "not necessary";
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break;
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case PCPU_BP_HARDEN_KIND_BPIALL:
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kind_str = "BPIALL";
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break;
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case PCPU_BP_HARDEN_KIND_ICIALLU:
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kind_str = "ICIALLU";
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break;
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default:
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panic("Unknown BP hardering kind (%d).", kind);
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}
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printf("CPU(%d) applied BP hardening: %s\n", PCPU_GET(cpuid),
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kind_str);
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}
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return;
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unkonown_mitigation:
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PCPU_SET(bp_harden_kind, PCPU_BP_HARDEN_KIND_NONE);
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spectre_v2_safe = 0;
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return;
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actlr_err:
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PCPU_SET(bp_harden_kind, PCPU_BP_HARDEN_KIND_NONE);
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spectre_v2_safe = 0;
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printf("!!!WARNING!!! CPU(%d) is vulnerable to speculative branch "
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"attacks. !!!\n"
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"We cannot enable required bit(s) in ACTRL register\n"
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"because it's locked by secure monitor and/or firmware.\n",
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PCPU_GET(cpuid));
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}
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void
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cpuinfo_init_bp_hardening(void)
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{
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/*
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* Store original unmodified ACTRL, so we can restore it when
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* BP hardening is disabled by sysctl.
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*/
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PCPU_SET(original_actlr, cp15_actlr_get());
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handle_bp_hardening(true);
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}
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static void
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bp_hardening_action(void *arg)
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{
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handle_bp_hardening(disable_bp_hardening == 0);
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}
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static int
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sysctl_disable_bp_hardening(SYSCTL_HANDLER_ARGS)
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{
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int rv;
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rv = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2, req);
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if (!rv && req->newptr) {
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spectre_v2_safe = 1;
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dmb();
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#ifdef SMP
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smp_rendezvous_cpus(all_cpus, smp_no_rendezvous_barrier,
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bp_hardening_action, NULL, NULL);
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#else
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bp_hardening_action(NULL);
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#endif
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}
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return (rv);
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}
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SYSCTL_PROC(_machdep, OID_AUTO, disable_bp_hardening,
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CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
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&disable_bp_hardening, 0, sysctl_disable_bp_hardening, "I",
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"Disable BP hardening mitigation.");
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SYSCTL_INT(_machdep, OID_AUTO, spectre_v2_safe, CTLFLAG_RD,
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&spectre_v2_safe, 0, "System is safe to Spectre Version 2 attacks");
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#endif /* __ARM_ARCH >= 6 */
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@ -33,6 +33,7 @@ __FBSDID("$FreeBSD$");
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#include <sys/cpuset.h>
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#include <sys/systm.h>
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#include <sys/assym.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/mbuf.h>
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#include <sys/vmmeter.h>
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@ -136,6 +137,10 @@ ASSYM(PCB_VFPSTATE, offsetof(struct pcb, pcb_vfpstate));
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#if __ARM_ARCH >= 6
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ASSYM(PC_CURPMAP, offsetof(struct pcpu, pc_curpmap));
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ASSYM(PC_BP_HARDEN_KIND, offsetof(struct pcpu, pc_bp_harden_kind));
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ASSYM(PCPU_BP_HARDEN_KIND_NONE, PCPU_BP_HARDEN_KIND_NONE);
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ASSYM(PCPU_BP_HARDEN_KIND_BPIALL, PCPU_BP_HARDEN_KIND_BPIALL);
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ASSYM(PCPU_BP_HARDEN_KIND_ICIALLU, PCPU_BP_HARDEN_KIND_ICIALLU);
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#endif
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ASSYM(PAGE_SIZE, PAGE_SIZE);
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@ -1264,6 +1264,8 @@ initarm(struct arm_boot_params *abp)
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msgbufinit(msgbufp, msgbufsize);
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dbg_monitor_init();
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kdb_init();
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/* Apply possible BP hardening. */
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cpuinfo_init_bp_hardening();
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return ((void *)STACKALIGN(thread0.td_pcb));
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}
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@ -201,6 +201,9 @@ init_secondary(int cpu)
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/* Configure the interrupt controller */
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intr_pic_init_secondary();
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/* Apply possible BP hardening */
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cpuinfo_init_bp_hardening();
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mtx_lock_spin(&ap_boot_mtx);
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atomic_add_rel_32(&smp_cpus, 1);
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@ -145,7 +145,16 @@ ENTRY(cpu_context_switch)
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* predictors and Requirements for branch predictor maintenance
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* operations sections.
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*/
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mcr CP15_BPIALL /* flush entire Branch Target Cache */
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/*
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* Additionally, to mitigate mistrained branch predictor attack
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* we must invalidate it on affected CPUs. Unfortunately, BPIALL
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* is effectively NOP on Cortex-A15 so it needs special treatment.
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*/
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ldr r0, [r8, #PC_BP_HARDEN_KIND]
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cmp r0, #PCPU_BP_HARDEN_KIND_ICIALLU
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mcrne CP15_BPIALL /* Flush entire Branch Target Cache */
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mcreq CP15_ICIALLU /* This is the only way how to flush */
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/* Branch Target Cache on Cortex-A15. */
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DSB
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mov pc, lr
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END(cpu_context_switch)
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@ -287,6 +287,7 @@ abort_handler(struct trapframe *tf, int prefetch)
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struct vmspace *vm;
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vm_prot_t ftype;
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bool usermode;
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int bp_harden;
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#ifdef INVARIANTS
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void *onfault;
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#endif
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@ -303,6 +304,20 @@ abort_handler(struct trapframe *tf, int prefetch)
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idx = FSR_TO_FAULT(fsr);
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usermode = TRAPF_USERMODE(tf); /* Abort came from user mode? */
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/*
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* Apply BP hardening by flushing the branch prediction cache
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* for prefaults on kernel addresses.
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*/
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if (__predict_false(prefetch && far > VM_MAXUSER_ADDRESS &&
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(idx == FAULT_TRAN_L2 || idx == FAULT_PERM_L2))) {
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bp_harden = PCPU_GET(bp_harden_kind);
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if (bp_harden == PCPU_BP_HARDEN_KIND_BPIALL)
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_CP15_BPIALL();
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else if (bp_harden == PCPU_BP_HARDEN_KIND_ICIALLU)
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_CP15_ICIALLU();
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}
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if (usermode)
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td->td_frame = tf;
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@ -49,6 +49,7 @@
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#define CPU_ARCH_CORTEX_A57 0xD07
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#define CPU_ARCH_CORTEX_A72 0xD08
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#define CPU_ARCH_CORTEX_A73 0xD09
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#define CPU_ARCH_CORTEX_A75 0xD0A
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/* QCOM */
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@ -125,6 +126,7 @@ extern struct cpuinfo cpuinfo;
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void cpuinfo_init(void);
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#if __ARM_ARCH >= 6
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void cpuinfo_init_bp_hardening(void);
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void cpuinfo_reinit_mmu(uint32_t ttb);
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#endif
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#endif /* _MACHINE_CPUINFO_H_ */
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@ -44,6 +44,10 @@ struct vmspace;
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#endif /* _KERNEL */
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#if __ARM_ARCH >= 6
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/* Branch predictor hardening method */
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#define PCPU_BP_HARDEN_KIND_NONE 0
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#define PCPU_BP_HARDEN_KIND_BPIALL 1
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#define PCPU_BP_HARDEN_KIND_ICIALLU 2
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#define PCPU_MD_FIELDS \
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unsigned int pc_vfpsid; \
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@ -59,7 +63,9 @@ struct vmspace;
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void *pc_qmap_pte2p; \
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unsigned int pc_dbreg[32]; \
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int pc_dbreg_cmd; \
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char __pad[155]
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int pc_bp_harden_kind; \
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uint32_t pc_original_actlr; \
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char __pad[147]
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#else
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#define PCPU_MD_FIELDS \
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char __pad[93]
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