Initialise the watchdog and UART frequencies.

For all pre-AR933x chips, the frequency is just the APB frequency.
For the AR933x, the UART frequency is different but we just hacked around
it.

For the AR934x, there's a different PLL setting for these, so they have
to be broken out.

sys/mips/atheros/ar71xx_chip.c

@@ -78,6 +78,8 @@ __FBSDID("$FreeBSD$");
 uint32_t u_ar71xx_cpu_freq;
 uint32_t u_ar71xx_ahb_freq;
 uint32_t u_ar71xx_ddr_freq;
+uint32_t u_ar71xx_uart_freq;
+uint32_t u_ar71xx_wdt_freq;
 uint32_t u_ar71xx_refclk;
 
 static void
@@ -107,6 +109,8 @@ ar71xx_chip_detect_sys_frequency(void)
 
 	div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
 	u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
+	u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div;
+	u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div;
 }
 
 /*

sys/mips/atheros/ar724x_chip.c

@@ -90,6 +90,8 @@ ar724x_chip_detect_sys_frequency(void)
 
 	div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
 	u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
+	u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div;
+	u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div;
 }
 
 static void

sys/mips/atheros/ar91xx_chip.c

@@ -84,6 +84,8 @@ ar91xx_chip_detect_sys_frequency(void)
 
 	div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
 	u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
+	u_ar71xx_uart_freq = u_ar71xx_cpu_freq / div;
+	u_ar71xx_wdt_freq = u_ar71xx_cpu_freq / div;
 }
 
 static void

sys/mips/atheros/ar933x_chip.c

@@ -114,6 +114,10 @@ ar933x_chip_detect_sys_frequency(void)
 		     AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
 		u_ar71xx_ahb_freq = freq / t;
 	}
+
+	/* XXX uart should be the refclk, no? */
+	u_ar71xx_uart_freq = u_ar71xx_ahb_freq;
+	u_ar71xx_wdt_freq = u_ar71xx_ahb_freq;
 }
 
 static void