Don't operate on the parent of the PCI node. It's the PCI node itself
that represents the host controller. This makes the FDT PCI support working an a bare-bones manner. This needs a lot more work, of which the beginning are at the end of the file, compiled-out with #if 0. The intend being that both the Marvell PCIE and Freescale PCI/PCIX/PCIE duplicate the same platform-independent domain initialization, that should be moved into an unified implementation in the FDT code. Handling of resources requires help from the platform. A unified implementation allows us to properly support PCI devices listed in the device tree and configured according to the device tree specification. Sponsored by: Juniper Networks
This commit is contained in:
marcel
parent
9ac3b7b64a
commit
6e31b7a52f
@ -39,10 +39,12 @@ __FBSDID("$FreeBSD$");
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#include <sys/malloc.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/pci/pcireg.h>
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#include <machine/fdt.h>
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#include "ofw_bus_if.h"
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#include "pcib_if.h"
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#define DEBUG
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#undef DEBUG
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@ -156,35 +158,17 @@ int
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fdt_pci_ranges(phandle_t node, struct fdt_pci_range *io_space,
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struct fdt_pci_range *mem_space)
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{
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struct fdt_pci_range par_io_space, par_mem_space;
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u_long base;
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int err;
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debugf("Processing parent PCI node: %x\n", node);
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if ((err = fdt_pci_ranges_decode(OF_parent(node), &par_io_space,
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&par_mem_space)) != 0) {
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debugf("Processing PCI node: %x\n", node);
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if ((err = fdt_pci_ranges_decode(node, io_space, mem_space)) != 0) {
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debugf("could not decode parent PCI node 'ranges'\n");
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return (err);
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}
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debugf("Processing PCI sub node: %x\n", node);
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if ((err = fdt_pci_ranges_decode(node, io_space, mem_space)) != 0) {
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debugf("could not decode PCI subnode 'ranges'\n");
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return (err);
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}
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base = io_space->base_parent & 0x000fffff;
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base += par_io_space.base_parent;
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io_space->base_parent = base;
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base = mem_space->base_parent & 0x000fffff;
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base += par_mem_space.base_parent;
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mem_space->base_parent = base;
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debugf("Post fixup dump:\n");
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fdt_pci_range_dump(io_space);
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fdt_pci_range_dump(mem_space);
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return (0);
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}
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@ -223,25 +207,25 @@ int
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fdt_pci_intr_info(phandle_t node, struct fdt_pci_intr *intr_info)
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{
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void *map, *mask;
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phandle_t pci_par;
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int intr_cells, addr_cells;
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int len;
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int acells, icells;
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int error, len;
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addr_cells = fdt_parent_addr_cells(node);
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error = fdt_addr_cells(node, &acells);
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if (error)
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return (error);
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pci_par = OF_parent(node);
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intr_cells = fdt_interrupt_cells(pci_par);
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icells = fdt_interrupt_cells(node);
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/*
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* Retrieve the interrupt map and mask properties.
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*/
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len = OF_getprop_alloc(pci_par, "interrupt-map-mask", 1, &mask);
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if (len / sizeof(pcell_t) != (addr_cells + intr_cells)) {
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len = OF_getprop_alloc(node, "interrupt-map-mask", 1, &mask);
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if (len / sizeof(pcell_t) != (acells + icells)) {
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debugf("bad mask len = %d\n", len);
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goto err;
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}
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len = OF_getprop_alloc(pci_par, "interrupt-map", 1, &map);
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len = OF_getprop_alloc(node, "interrupt-map", 1, &map);
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if (len <= 0) {
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debugf("bad map len = %d\n", len);
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goto err;
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@ -250,8 +234,10 @@ fdt_pci_intr_info(phandle_t node, struct fdt_pci_intr *intr_info)
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intr_info->map_len = len;
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intr_info->map = map;
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intr_info->mask = mask;
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intr_info->addr_cells = addr_cells;
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intr_info->intr_cells = intr_cells;
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intr_info->addr_cells = acells;
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intr_info->intr_cells = icells;
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debugf("acells=%u, icells=%u, map_len=%u\n", acells, icells, len);
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return (0);
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err:
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@ -326,7 +312,8 @@ fdt_pci_route_intr(int bus, int slot, int func, int pin,
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trig, pol);
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#if defined(__powerpc__)
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powerpc_config_intr(INTR_VEC(intr_par, *interrupt), trig, pol);
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powerpc_config_intr(FDT_MAP_IRQ(intr_par, *interrupt), trig,
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pol);
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#endif
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return (0);
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@ -364,3 +351,218 @@ fdt_pci_devmap(phandle_t node, struct pmap_devmap *devmap, vm_offset_t io_va,
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return (0);
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}
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#endif
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#if 0
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static int
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fdt_pci_config_bar(device_t dev, int bus, int slot, int func, int bar)
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{
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}
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static int
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fdt_pci_config_normal(device_t dev, int bus, int slot, int func)
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{
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int bar;
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uint8_t command, intline, intpin;
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command = PCIB_READ_CONFIG(dev, bus, slot, func, PCIR_COMMAND, 1);
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command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
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PCIB_WRITE_CONFIG(dev, bus, slot, func, PCIR_COMMAND, command, 1);
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/* Program the base address registers. */
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bar = 0;
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while (bar <= PCIR_MAX_BAR_0)
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bar += fdt_pci_config_bar(dev, bus, slot, func, bar);
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/* Perform interrupt routing. */
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intpin = PCIB_READ_CONFIG(dev, bus, slot, func, PCIR_INTPIN, 1);
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intline = fsl_pcib_route_int(dev, bus, slot, func, intpin);
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PCIB_WRITE_CONFIG(dev, bus, slot, func, PCIR_INTLINE, intline, 1);
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command |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
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PCIB_WRITE_CONFIG(dev, bus, slot, func, PCIR_COMMAND, command, 1);
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}
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static int
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fdt_pci_config_bridge(device_t dev, int bus, int secbus, int slot, int func)
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{
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int maxbar;
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uint8_t command;
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command = PCIB_READ_CONFIG(dev, bus, slot, func, PCIR_COMMAND, 1);
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command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
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PCIB_WRITE_CONFIG(dev, bus, slot, func, PCIR_COMMAND, command, 1);
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/* Program the base address registers. */
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maxbar = (hdrtype & PCIM_HDRTYPE) ? 1 : 6;
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bar = 0;
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while (bar < maxbar)
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bar += fsl_pcib_init_bar(sc, bus, slot, func,
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bar);
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/* Perform interrupt routing. */
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intpin = fsl_pcib_read_config(sc->sc_dev, bus, slot,
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func, PCIR_INTPIN, 1);
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intline = fsl_pcib_route_int(sc, bus, slot, func,
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intpin);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_INTLINE, intline, 1);
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command |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_COMMAND, command, 1);
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/*
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* Handle PCI-PCI bridges
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*/
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class = fsl_pcib_read_config(sc->sc_dev, bus, slot,
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func, PCIR_CLASS, 1);
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subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot,
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func, PCIR_SUBCLASS, 1);
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/* Allow only proper PCI-PCI briges */
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if (class != PCIC_BRIDGE)
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continue;
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if (subclass != PCIS_BRIDGE_PCI)
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continue;
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secbus++;
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/* Program I/O decoder. */
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_IOBASEL_1, sc->sc_ioport.rm_start >> 8, 1);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_IOLIMITL_1, sc->sc_ioport.rm_end >> 8, 1);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_IOBASEH_1, sc->sc_ioport.rm_start >> 16, 2);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_IOLIMITH_1, sc->sc_ioport.rm_end >> 16, 2);
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/* Program (non-prefetchable) memory decoder. */
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_MEMBASE_1, sc->sc_iomem.rm_start >> 16, 2);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_MEMLIMIT_1, sc->sc_iomem.rm_end >> 16, 2);
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/* Program prefetchable memory decoder. */
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_PMBASEL_1, 0x0010, 2);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_PMLIMITL_1, 0x000f, 2);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_PMBASEH_1, 0x00000000, 4);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_PMLIMITH_1, 0x00000000, 4);
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/* Read currect bus register configuration */
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old_pribus = fsl_pcib_read_config(sc->sc_dev, bus,
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slot, func, PCIR_PRIBUS_1, 1);
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old_secbus = fsl_pcib_read_config(sc->sc_dev, bus,
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slot, func, PCIR_SECBUS_1, 1);
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old_subbus = fsl_pcib_read_config(sc->sc_dev, bus,
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slot, func, PCIR_SUBBUS_1, 1);
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if (bootverbose)
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printf("PCI: reading firmware bus numbers for "
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"secbus = %d (bus/sec/sub) = (%d/%d/%d)\n",
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secbus, old_pribus, old_secbus, old_subbus);
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new_pribus = bus;
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new_secbus = secbus;
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secbus = fsl_pcib_init(sc, secbus,
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(subclass == PCIS_BRIDGE_PCI) ? PCI_SLOTMAX : 0);
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new_subbus = secbus;
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if (bootverbose)
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printf("PCI: translate firmware bus numbers "
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"for secbus %d (%d/%d/%d) -> (%d/%d/%d)\n",
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secbus, old_pribus, old_secbus, old_subbus,
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new_pribus, new_secbus, new_subbus);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_PRIBUS_1, new_pribus, 1);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_SECBUS_1, new_secbus, 1);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_SUBBUS_1, new_subbus, 1);
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}
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static int
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fdt_pci_config_slot(device_t dev, int bus, int secbus, int slot)
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{
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int func, maxfunc;
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uint16_t vendor;
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uint8_t hdrtype;
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maxfunc = 0;
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for (func = 0; func <= maxfunc; func++) {
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hdrtype = PCIB_READ_CONFIG(dev, bus, slot, func,
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PCIR_HDRTYPE, 1);
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if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
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continue;
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if (func == 0 && (hdrtype & PCIM_MFDEV))
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maxfunc = PCI_FUNCMAX;
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vendor = PCIB_READ_CONFIG(dev, bus, slot, func,
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PCIR_VENDOR, 2);
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if (vendor == 0xffff)
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continue;
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if ((hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_NORMAL)
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fdt_pci_config_normal(dev, bus, slot, func);
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else
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secbus = fdt_pci_config_bridge(dev, bus, secbus,
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slot, func);
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}
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return (secbus);
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}
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static int
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fdt_pci_config_bus(device_t dev, int bus, int maxslot)
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{
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int func, maxfunc, secbus, slot;
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secbus = bus;
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for (slot = 0; slot <= maxslot; slot++)
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secbus = fdt_pci_config_slot(dev, bus, secbus, slot);
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return (secbus);
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}
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int
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fdt_pci_config_domain(device_t dev)
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{
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pcell_t bus_range[2];
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phandle_t root;
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int bus, error, maxslot;
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root = ofw_bus_get_node(dev);
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if (root == 0)
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return (EINVAL);
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if (!fdt_is_type(root, "pci"))
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return (EINVAL);
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/*
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* Determine the bus number of the root in this domain.
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* Lacking any information, this will be bus 0.
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* Write the bus number to the bus device, using the IVAR.
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*/
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if ((OF_getprop(root, "bus-range", bus_range, sizeof(bus_range)) <= 0)
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bus = 0;
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else
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bus = fdt32_to_cpu(bus_range[0]);
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error = BUS_WRITE_IVAR(dev, NULL, PCIB_IVAR_BUS, bus);
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if (error)
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return (error);
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/* Get the maximum slot number for bus-enumeration. */
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maxslot = PCIB_MAXSLOTS(dev);
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bus = fdt_pci_config_bus(dev, bus, maxslot);
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return (0);
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}
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#endif
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