From 6e4d0251238525ed116e919ac938b6cecf3f55a9 Mon Sep 17 00:00:00 2001 From: jchandra Date: Thu, 24 Jan 2013 11:42:16 +0000 Subject: [PATCH] Little-endian fix for PCI on Broadcom XLP. Update the function xlp_pcib_hardware_swap_enable() to do nothing when BYTE_ORDER is not BIG_ENDIAN. PCIe hardware swap is not requred in little-endian mode as the endianness matches that of CPU. --- sys/mips/nlm/xlp_pci.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/sys/mips/nlm/xlp_pci.c b/sys/mips/nlm/xlp_pci.c index 0610a156f4f8..23bd46cd2825 100644 --- a/sys/mips/nlm/xlp_pci.c +++ b/sys/mips/nlm/xlp_pci.c @@ -487,12 +487,14 @@ xlp_pcib_write_config(device_t dev, u_int b, u_int s, u_int f, } /* - * Enable byte swap in hardware. Program a link's PCIe SWAP regions - * from the link's IO and MEM address ranges. + * Enable byte swap in hardware when compiled big-endian. + * Programs a link's PCIe SWAP regions from the link's IO and MEM address + * ranges. */ static void xlp_pcib_hardware_swap_enable(int node, int link) { +#if BYTE_ORDER == BIG_ENDIAN uint64_t bbase, linkpcibase; uint32_t bar; int pcieoffset; @@ -514,6 +516,7 @@ xlp_pcib_hardware_swap_enable(int node, int link) bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_LIMIT0 + link); nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar | 0xFFF); +#endif } static int