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Fix the pl011 driver to work when the uart will write in zero cycles. This

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is the case, depending on the options, in some of the ARM hardware
simulators. In these cases we don't get an interrupt so will need to
schedule the task to write more data to the uart.

MFC after:	1 week
Sponsored by:	The FreeBSD Foundation
This commit is contained in:
andrew 2015-03-03 09:48:19 +00:00
parent efdf3024fd
commit 6e4d5a7168
1 changed files with 13 additions and 5 deletions
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18
sys/dev/uart/uart_dev_pl011.c
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@ -452,15 +452,23 @@ uart_pl011_bus_transmit(struct uart_softc *sc)
__uart_setreg(bas, UART_DR, sc->sc_txbuf[i]);
uart_barrier(bas);
}
sc->sc_txbusy = 1;
/* Enable TX interrupt */
reg = __uart_getreg(bas, UART_IMSC);
reg |= (UART_TXEMPTY);
__uart_setreg(bas, UART_IMSC, reg);
/* If not empty wait until it is */
if ((__uart_getreg(bas, UART_FR) & FR_TXFE) != FR_TXFE) {
sc->sc_txbusy = 1;
/* Enable TX interrupt */
reg = __uart_getreg(bas, UART_IMSC);
reg |= (UART_TXEMPTY);
__uart_setreg(bas, UART_IMSC, reg);
}
uart_unlock(sc->sc_hwmtx);
/* No interrupt expected, schedule the next fifo write */
if (!sc->sc_txbusy)
uart_sched_softih(sc, SER_INT_TXIDLE);
return (0);
}