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Bring over some AR9271 register definitions from the QCA HAL.

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Obtained from:	Qualcomm Atheros
This commit is contained in:
adrian 2013-04-15 17:58:11 +00:00
parent 59c782b807
commit 6f9077d752
1 changed files with 19 additions and 0 deletions
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19
sys/dev/ath/ath_hal/ar5416/ar5416reg.h
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@ -603,6 +603,25 @@
#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000
#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000
/* K2 (9271) */
#define AR9271_CLOCK_CONTROL 0x50040
#define AR9271_CLOCK_SELECTION_22 0x0
#define AR9271_CLOCK_SELECTION_88 0x1
#define AR9271_CLOCK_SELECTION_44 0x2
#define AR9271_CLOCK_SELECTION_117 0x4
#define AR9271_CLOCK_SELECTION_OSC_40 0x6
#define AR9271_CLOCK_SELECTION_RTC 0x7
#define AR9271_SPI_SEL 0x100
#define AR9271_UART_SEL 0x200
#define AR9271_RESET_POWER_DOWN_CONTROL 0x50044
#define AR9271_RADIO_RF_RST 0x20
#define AR9271_GATE_MAC_CTL 0x4000
#define AR9271_MAIN_PLL_PWD_CTL 0x40000
#define AR9271_CLKMISC 0x4090
#define AR9271_OSC_to_10M_EN 0x00000001
/*
* AR5212 defines the MAC revision mask as 0xF, but both ath9k and
* the Atheros HAL define it as 0x7.