Add a workaround for quirky PCI devices that set the intpin register to
0, but use this mechanism to generate interrupts. Preserve the child device when setting up and tearing down interrupts. Some style nits.
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@ -32,7 +32,7 @@
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*/
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/*
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* Support for `psycho' and `psycho+' UPA to PCI bridge and
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* Support for `psycho' and `psycho+' UPA to PCI bridge and
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* UltraSPARC IIi and IIe `sabre' PCI controllers.
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*/
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@ -192,7 +192,7 @@ struct psycho_clr {
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* and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while
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* "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You
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* will usually find a "psycho+" since I don't think the original "psycho"
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* ever shipped, and if it did it would be in the U30.
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* ever shipped, and if it did it would be in the U30.
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*
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* Each "psycho" PCI bus appears as a separate OFW node, but since they are
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* both part of the same IC, they only have a single register space. As such,
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@ -204,7 +204,7 @@ struct psycho_clr {
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* numbers on some machines.
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*
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* On UltraII machines, there can be any number of "psycho+" ICs, each
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* providing two PCI buses.
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* providing two PCI buses.
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*
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*
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* XXXX The psycho/sabre node has an `interrupts' attribute. They contain
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@ -255,7 +255,7 @@ psycho_probe(device_t dev)
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* - figure out the IGN.
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* - find our partner psycho
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* - configure ourselves
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* - bus range, bus,
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* - bus range, bus,
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* - interrupt map,
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* - setup the chipsets.
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* - if we're the first of the pair, initialise the IOMMU, otherwise
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@ -579,7 +579,7 @@ psycho_attach(device_t dev)
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*/
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ofw_pci_init_intr(dev, sc->sc_node, sc->sc_intrmap, sc->sc_nintrmap,
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&sc->sc_intrmapmsk);
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device_add_child(dev, "pci", device_get_unit(dev));
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return (bus_generic_attach(dev));
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}
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@ -666,7 +666,7 @@ psycho_ue(void *arg)
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sc->sc_regs->ue_int_clr = 0;
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/* It's uncorrectable. Dump the regs and panic. */
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panic("%s: uncorrectable DMA error AFAR %llx AFSR %llx\n",
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device_get_name(sc->sc_dev),
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device_get_name(sc->sc_dev),
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(long long)regs->psy_ue_afar, (long long)regs->psy_ue_afsr);
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}
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@ -679,7 +679,7 @@ psycho_ce(void *arg)
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sc->sc_regs->ce_int_clr = 0;
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/* It's correctable. Dump the regs and continue. */
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printf("%s: correctable DMA error AFAR %llx AFSR %llx\n",
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device_get_name(sc->sc_dev),
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device_get_name(sc->sc_dev),
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(long long)regs->psy_ce_afar, (long long)regs->psy_ce_afsr);
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}
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@ -692,7 +692,7 @@ psycho_bus_a(void *arg)
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sc->sc_regs->pciaerr_int_clr = 0;
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/* It's uncorrectable. Dump the regs and panic. */
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panic("%s: PCI bus A error AFAR %lx AFSR %lx\n",
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device_get_name(sc->sc_dev),
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device_get_name(sc->sc_dev),
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regs->psy_pcictl[0].pci_afar, regs->psy_pcictl[0].pci_afsr);
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}
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@ -805,6 +805,28 @@ psycho_maxslots(device_t dev)
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return (31);
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}
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/*
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* Keep a table of quirky PCI devices that need fixups before the MI PCI code
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* creates the resource lists. This needs to be moved around once other bus
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* drivers are added. Moving it to the MI code should maybe be reconsidered
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* if one of these devices appear in non-sparc64 boxen. It's likely that not
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* all BIOSes/firmwares can deal with them.
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*/
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struct psycho_dquirk {
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u_int32_t dq_devid;
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int dq_quirk;
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};
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/* Quirk types. May be or'ed together. */
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#define DQT_BAD_INTPIN 1 /* Intpin reg 0, but intpin used */
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static struct psycho_dquirk dquirks[] = {
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{ 0x1001108e, DQT_BAD_INTPIN }, /* Sun HME (PCIO func. 1) */
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{ 0x1101108e, DQT_BAD_INTPIN }, /* Sun GEM (PCIO2 func. 1) */
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};
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#define NDQUIRKS (sizeof(dquirks) / sizeof(dquirks[0]))
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static u_int32_t
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psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
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int width)
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@ -812,15 +834,17 @@ psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
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struct psycho_softc *sc;
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bus_space_handle_t bh;
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u_long offset = 0;
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u_int32_t r;
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u_int32_t r, devid;
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int i;
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/*
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* The psycho bridge does not tolerate accesses to unconfigured PCI
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* devices' or function's config space, so look up the device in the
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* first, and if it is not present, return a value that will make the
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* detection think that there is no device here. This is somehow ugly...
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* firmware device tree first, and if it is not present, return a value
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* that will make the detection code think that there is no device here.
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* This is ugly...
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*/
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if (ofw_pci_find_node(bus, slot, func) == 0)
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if (reg == 0 && ofw_pci_find_node(bus, slot, func) == 0)
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return (0xffffffff);
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sc = (struct psycho_softc *)device_get_softc(dev);
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offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
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@ -838,6 +862,27 @@ psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
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default:
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panic("psycho_read_config: bad width");
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}
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if (reg == PCIR_INTPIN && r == 0) {
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/* Check for DQT_BAD_INTPIN quirk. */
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devid = psycho_read_config(dev, bus, slot, func,
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PCIR_DEVVENDOR, 4);
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for (i = 0; i < NDQUIRKS; i++) {
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if (dquirks[i].dq_devid == devid) {
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/*
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* Need to set the intpin to a value != 0 so
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* that the MI code will think that this device
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* has an interrupt.
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* Just use 1 (intpin a) for now. This is, of
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* course, bogus, but since interrupts are
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* routed in advance, this does not really
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* matter.
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*/
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if ((dquirks[i].dq_quirk & DQT_BAD_INTPIN) != 0)
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r = 1;
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break;
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}
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}
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}
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return (r);
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}
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@ -944,7 +989,7 @@ psycho_setup_intr(device_t dev, device_t child,
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* XXX We only compare INOs rather than IGNs since the firmware may
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* not provide the IGN and the IGN is constant for all device on that
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* PCI controller. This could cause problems for the FFB/external
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* interrupt which has a full vector that can be set arbitrarily.
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* interrupt which has a full vector that can be set arbitrarily.
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*/
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ino = INTINO(vec);
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@ -964,15 +1009,15 @@ psycho_setup_intr(device_t dev, device_t child,
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/* Disable the interrupt while we fiddle with it */
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*intrmapptr &= ~INTMAP_V;
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membar(Sync);
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error = bus_setup_intr(dev, ires, flags, psycho_intr_stub, pc,
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cookiep);
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error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags,
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psycho_intr_stub, pc, cookiep);
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if (error != 0) {
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free(pc, M_DEVBUF);
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return (error);
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}
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pc->pci_cookie = *cookiep;
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*cookiep = pc;
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/*
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* Clear the interrupt, it might have been triggered before it was
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* set up.
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@ -996,7 +1041,8 @@ psycho_teardown_intr(device_t dev, device_t child,
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int error;
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pc = (struct psycho_clr *)cookie;
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error = bus_teardown_intr(dev, vec, pc->pci_cookie);
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error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec,
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pc->pci_cookie);
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/*
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* Don't disable the interrupt for now, so that stray interupts get
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* detected...
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@ -1056,7 +1102,7 @@ psycho_alloc_resource(device_t bus, device_t child, int type, int *rid,
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bh += rman_get_start(rv);
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rman_set_bustag(rv, bt);
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rman_set_bushandle(rv, bh);
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rman_set_bushandle(rv, bh);
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if (needactivate) {
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if (bus_activate_resource(child, type, *rid, rv)) {
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@ -1064,7 +1110,7 @@ psycho_alloc_resource(device_t bus, device_t child, int type, int *rid,
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return (NULL);
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}
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}
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return (rv);
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}
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@ -1082,7 +1128,7 @@ static int
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psycho_deactivate_resource(device_t bus, device_t child, int type, int rid,
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struct resource *r)
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{
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if (type == SYS_RES_IRQ)
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return (bus_deactivate_resource(bus, type, rid, r));
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return (rman_deactivate_resource(r));
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