Fix issues with zeroing and fetching the counters, on x86 and ppc64.
Issues were noted by Bruce Evans and are present on all architectures. On i386, a counter fetch should use atomic read of 64bit value, otherwise carry from the increment on other CPU could be lost for the given fetch, making error of 2^32. If 64bit read (cmpxchg8b) is not available on the machine, it cannot be SMP and it is enough to disable preemption around read to avoid the split read. On x86 the counter increment is not atomic on purpose, which makes it possible for the store of the incremented result to override just zeroed per-cpu slot. The effect would be a counter going off by arbitrary value after zeroing. Perform the counter zeroing on the same processor which does the increments, making the operations mutually exclusive. On i386, same as for the fetching, if the cmpxchg8b is not available, machine is not SMP and we disable preemption for zeroing. PowerPC64 is treated the same as amd64. For other architectures, the changes made to allow the compilation to succeed, without fixing the issues with zeroing or fetching. It should be possible to handle them by using the 64bit loads and stores atomic WRT preemption (assuming the architectures also converted from using critical sections to proper asm). If architecture does not provide the facility, using global (spin) mutex would be non-optimal but working solution. Noted by: bde Sponsored by: The FreeBSD Foundation
This commit is contained in:
Konstantin Belousov
parent
7476f6973c
commit
70a7dd5d5b
@ -36,6 +36,44 @@ extern struct pcpu __pcpu[1];
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#define counter_enter() do {} while (0)
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#define counter_exit() do {} while (0)
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#ifdef IN_SUBR_COUNTER_C
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static inline uint64_t
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counter_u64_read_one(uint64_t *p, int cpu)
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{
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return (*(uint64_t *)((char *)p + sizeof(struct pcpu) * cpu));
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}
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static inline uint64_t
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counter_u64_fetch_inline(uint64_t *p)
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{
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uint64_t r;
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int i;
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r = 0;
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for (i = 0; i < mp_ncpus; i++)
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r += counter_u64_read_one((uint64_t *)p, i);
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return (r);
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}
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static void
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counter_u64_zero_one_cpu(void *arg)
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{
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*((uint64_t *)((char *)arg + sizeof(struct pcpu) *
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PCPU_GET(cpuid))) = 0;
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}
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static inline void
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counter_u64_zero_inline(counter_u64_t c)
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{
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smp_rendezvous(smp_no_rendevous_barrier, counter_u64_zero_one_cpu,
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smp_no_rendevous_barrier, c);
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}
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#endif
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#define counter_u64_add_protected(c, i) counter_u64_add(c, i)
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static inline void
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@ -37,6 +37,46 @@
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#define counter_enter() critical_enter()
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#define counter_exit() critical_exit()
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#ifdef IN_SUBR_COUNTER_C
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/* XXXKIB non-atomic 64bit read */
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static inline uint64_t
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counter_u64_read_one(uint64_t *p, int cpu)
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{
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return (*(uint64_t *)((char *)p + sizeof(struct pcpu) * cpu));
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}
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static inline uint64_t
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counter_u64_fetch_inline(uint64_t *p)
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{
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uint64_t r;
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int i;
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r = 0;
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for (i = 0; i < mp_ncpus; i++)
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r += counter_u64_read_one((uint64_t *)p, i);
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return (r);
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}
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/* XXXKIB non-atomic 64bit store, might interrupt increment */
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static void
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counter_u64_zero_one_cpu(void *arg)
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{
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*((uint64_t *)((char *)arg + sizeof(struct pcpu) *
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PCPU_GET(cpuid))) = 0;
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}
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static inline void
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counter_u64_zero_inline(counter_u64_t c)
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{
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smp_rendezvous(smp_no_rendevous_barrier, counter_u64_zero_one_cpu,
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smp_no_rendevous_barrier, c);
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}
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#endif
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#define counter_u64_add_protected(c, inc) do { \
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CRITICAL_ASSERT(curthread); \
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*(uint64_t *)zpcpu_get(c) += (inc); \
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@ -67,6 +67,93 @@ counter_64_inc_8b(uint64_t *p, int64_t inc)
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: "memory", "cc", "eax", "edx", "ebx", "ecx");
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}
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#ifdef IN_SUBR_COUNTER_C
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static inline uint64_t
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counter_u64_read_one_8b(uint64_t *p)
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{
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uint32_t res_lo, res_high;
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__asm __volatile(
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"movl %%eax,%%ebx\n\t"
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"movl %%edx,%%ecx\n\t"
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"cmpxchg8b (%2)"
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: "=a" (res_lo), "=d"(res_high)
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: "SD" (p)
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: "cc", "ebx", "ecx");
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return (res_lo + ((uint64_t)res_high << 32));
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}
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static inline uint64_t
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counter_u64_fetch_inline(uint64_t *p)
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{
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uint64_t res;
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int i;
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res = 0;
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if ((cpu_feature & CPUID_CX8) == 0) {
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/*
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* The machines without cmpxchg8b are not SMP.
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* Disabling the preemption provides atomicity of the
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* counter reading, since update is done in the
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* critical section as well.
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*/
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critical_enter();
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for (i = 0; i < mp_ncpus; i++) {
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res += *(uint64_t *)((char *)p +
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sizeof(struct pcpu) * i);
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}
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critical_exit();
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} else {
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for (i = 0; i < mp_ncpus; i++)
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res += counter_u64_read_one_8b((uint64_t *)((char *)p +
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sizeof(struct pcpu) * i));
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}
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return (res);
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}
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static inline void
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counter_u64_zero_one_8b(uint64_t *p)
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{
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__asm __volatile(
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"movl (%0),%%eax\n\t"
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"movl 4(%0),%%edx\n"
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"xorl %%ebx,%%ebx\n\t"
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"xorl %%ecx,%%ecx\n\t"
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"1:\n\t"
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"cmpxchg8b (%0)\n\t"
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"jnz 1b"
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:
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: "SD" (p)
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: "memory", "cc", "eax", "edx", "ebx", "ecx");
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}
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static void
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counter_u64_zero_one_cpu(void *arg)
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{
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uint64_t *p;
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p = (uint64_t *)((char *)arg + sizeof(struct pcpu) * PCPU_GET(cpuid));
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counter_u64_zero_one_8b(p);
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}
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static inline void
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counter_u64_zero_inline(counter_u64_t c)
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{
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int i;
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if ((cpu_feature & CPUID_CX8) == 0) {
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critical_enter();
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for (i = 0; i < mp_ncpus; i++)
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*(uint64_t *)((char *)c + sizeof(struct pcpu) * i) = 0;
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critical_exit();
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} else {
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smp_rendezvous(smp_no_rendevous_barrier,
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counter_u64_zero_one_cpu, smp_no_rendevous_barrier, c);
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}
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}
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#endif
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#define counter_u64_add_protected(c, inc) do { \
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if ((cpu_feature & CPUID_CX8) == 0) { \
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CRITICAL_ASSERT(curthread); \
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@ -37,6 +37,45 @@
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#define counter_enter() critical_enter()
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#define counter_exit() critical_exit()
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#ifdef IN_SUBR_COUNTER_C
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static inline uint64_t
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counter_u64_read_one(uint64_t *p, int cpu)
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{
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return (*(uint64_t *)((char *)p + sizeof(struct pcpu) * cpu));
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}
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static inline uint64_t
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counter_u64_fetch_inline(uint64_t *p)
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{
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uint64_t r;
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int i;
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r = 0;
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for (i = 0; i < mp_ncpus; i++)
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r += counter_u64_read_one((uint64_t *)p, i);
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return (r);
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}
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/* XXXKIB might interrupt increment */
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static void
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counter_u64_zero_one_cpu(void *arg)
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{
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*((uint64_t *)((char *)arg + sizeof(struct pcpu) *
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PCPU_GET(cpuid))) = 0;
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}
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static inline void
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counter_u64_zero_inline(counter_u64_t c)
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{
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smp_rendezvous(smp_no_rendevous_barrier, counter_u64_zero_one_cpu,
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smp_no_rendevous_barrier, c);
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}
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#endif
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#define counter_u64_add_protected(c, inc) do { \
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CRITICAL_ASSERT(curthread); \
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*(uint64_t *)zpcpu_get(c) += (inc); \
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@ -29,34 +29,32 @@ __FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/counter.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#include <sys/sched.h>
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#include <sys/smp.h>
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#include <sys/sysctl.h>
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#include <vm/uma.h>
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#define IN_SUBR_COUNTER_C
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#include <sys/counter.h>
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static uma_zone_t uint64_pcpu_zone;
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void
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counter_u64_zero(counter_u64_t c)
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{
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int i;
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for (i = 0; i < mp_ncpus; i++)
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*(uint64_t *)((char *)c + sizeof(struct pcpu) * i) = 0;
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counter_u64_zero_inline(c);
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}
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uint64_t
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counter_u64_fetch(counter_u64_t c)
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{
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uint64_t r;
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int i;
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r = 0;
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for (i = 0; i < mp_ncpus; i++)
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r += *(uint64_t *)((char *)c + sizeof(struct pcpu) * i);
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return (r);
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return (counter_u64_fetch_inline(c));
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}
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counter_u64_t
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@ -37,6 +37,46 @@
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#define counter_enter() critical_enter()
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#define counter_exit() critical_exit()
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#ifdef IN_SUBR_COUNTER_C
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/* XXXKIB non-atomic 64bit read on 32bit */
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static inline uint64_t
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counter_u64_read_one(uint64_t *p, int cpu)
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{
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return (*(uint64_t *)((char *)p + sizeof(struct pcpu) * cpu));
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}
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static inline uint64_t
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counter_u64_fetch_inline(uint64_t *p)
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{
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uint64_t r;
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int i;
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r = 0;
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for (i = 0; i < mp_ncpus; i++)
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r += counter_u64_read_one((uint64_t *)p, i);
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return (r);
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}
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/* XXXKIB non-atomic 64bit store on 32bit, might interrupt increment */
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static void
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counter_u64_zero_one_cpu(void *arg)
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{
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*((uint64_t *)((char *)arg + sizeof(struct pcpu) *
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PCPU_GET(cpuid))) = 0;
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}
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static inline void
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counter_u64_zero_inline(counter_u64_t c)
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{
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smp_rendezvous(smp_no_rendevous_barrier, counter_u64_zero_one_cpu,
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smp_no_rendevous_barrier, c);
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}
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#endif
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#define counter_u64_add_protected(c, inc) do { \
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CRITICAL_ASSERT(curthread); \
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*(uint64_t *)zpcpu_get(c) += (inc); \
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@ -39,6 +39,44 @@
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#define counter_enter() do {} while (0)
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#define counter_exit() do {} while (0)
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#ifdef IN_SUBR_COUNTER_C
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static inline uint64_t
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counter_u64_read_one(uint64_t *p, int cpu)
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{
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return (*(uint64_t *)((char *)p + sizeof(struct pcpu) * cpu));
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}
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static inline uint64_t
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counter_u64_fetch_inline(uint64_t *p)
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{
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uint64_t r;
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int i;
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r = 0;
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for (i = 0; i < mp_ncpus; i++)
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r += counter_u64_read_one((uint64_t *)p, i);
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return (r);
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}
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static void
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counter_u64_zero_one_cpu(void *arg)
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{
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*((uint64_t *)((char *)arg + sizeof(struct pcpu) *
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PCPU_GET(cpuid))) = 0;
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}
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static inline void
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counter_u64_zero_inline(counter_u64_t c)
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{
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smp_rendezvous(smp_no_rendevous_barrier, counter_u64_zero_one_cpu,
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smp_no_rendevous_barrier, c);
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}
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#endif
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#define counter_u64_add_protected(c, i) counter_u64_add(c, i)
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extern struct pcpu __pcpu[MAXCPU];
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@ -65,6 +103,46 @@ counter_u64_add(counter_u64_t c, int64_t inc)
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#define counter_enter() critical_enter()
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#define counter_exit() critical_exit()
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#ifdef IN_SUBR_COUNTER_C
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/* XXXKIB non-atomic 64bit read */
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static inline uint64_t
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counter_u64_read_one(uint64_t *p, int cpu)
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{
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return (*(uint64_t *)((char *)p + sizeof(struct pcpu) * cpu));
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}
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static inline uint64_t
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counter_u64_fetch_inline(uint64_t *p)
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{
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uint64_t r;
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int i;
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r = 0;
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for (i = 0; i < mp_ncpus; i++)
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r += counter_u64_read_one((uint64_t *)p, i);
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return (r);
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}
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/* XXXKIB non-atomic 64bit store, might interrupt increment */
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static void
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counter_u64_zero_one_cpu(void *arg)
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{
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*((uint64_t *)((char *)arg + sizeof(struct pcpu) *
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PCPU_GET(cpuid))) = 0;
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}
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static inline void
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counter_u64_zero_inline(counter_u64_t c)
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{
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smp_rendezvous(smp_no_rendevous_barrier, counter_u64_zero_one_cpu,
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smp_no_rendevous_barrier, c);
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}
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#endif
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#define counter_u64_add_protected(c, inc) do { \
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CRITICAL_ASSERT(curthread); \
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*(uint64_t *)zpcpu_get(c) += (inc); \
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@ -37,6 +37,45 @@
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#define counter_enter() critical_enter()
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#define counter_exit() critical_exit()
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#ifdef IN_SUBR_COUNTER_C
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static inline uint64_t
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counter_u64_read_one(uint64_t *p, int cpu)
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{
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return (*(uint64_t *)((char *)p + sizeof(struct pcpu) * cpu));
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}
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static inline uint64_t
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counter_u64_fetch_inline(uint64_t *p)
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{
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uint64_t r;
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int i;
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r = 0;
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for (i = 0; i < mp_ncpus; i++)
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r += counter_u64_read_one((uint64_t *)p, i);
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return (r);
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}
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/* XXXKIB might interrupt increment */
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static void
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counter_u64_zero_one_cpu(void *arg)
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{
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*((uint64_t *)((char *)arg + sizeof(struct pcpu) *
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PCPU_GET(cpuid))) = 0;
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}
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static inline void
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counter_u64_zero_inline(counter_u64_t c)
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{
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smp_rendezvous(smp_no_rendevous_barrier, counter_u64_zero_one_cpu,
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smp_no_rendevous_barrier, c);
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}
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#endif
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#define counter_u64_add_protected(c, inc) do { \
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CRITICAL_ASSERT(curthread); \
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*(uint64_t *)zpcpu_get(c) += (inc); \
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