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Fix the last remaining problem encountered by KSE: apparently it is

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not guaranteed that the RSE writes the NaT collection immediately,
sort of atomically, to the backing store when it writes the register
immediately prior to the NaT collection point. This means that we
cannot assume that the low 9 bits of the backingstore pointer do not
point to the NaT collection. This is rather a surprise and I don't
know at this time if it's a bug in the Merced or that it's actually
a valid condition of the architecture. A quick scan over the sources
does not indicate that we depend on the false assumption elsewhere,
but it's something to keep in mind.

The fix is to write the saved contents of the ar.rnat register to
the backingstore prior to entering the loop that copies the dirty
registers from the kernel stack to the user stack.
This commit is contained in:
Marcel Moolenaar 2003-09-20 20:34:58 +00:00
parent cf3153c9c9
commit 719325db8e
1 changed files with 5 additions and 1 deletions
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6
sys/ia64/ia64/machdep.c
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@ -1076,8 +1076,12 @@ get_mcontext(struct thread *td, mcontext_t *mc, int clear_ret)
if (bspst - td->td_kstack < s.ndirty)
__asm __volatile("flushrs;;");
__asm __volatile("mov ar.rsc=3");
ustk = (uint64_t*)s.bspstore;
kstk = (uint64_t*)td->td_kstack;
ustk = (uint64_t*)s.bspstore;
if ((s.bspstore & 0x1ff) == 0x1f8) {
suword64(ustk++, s.rnat);
s.rnat = 0;
}
while (s.ndirty > 0) {
suword64(ustk++, *kstk++);
if (((uintptr_t)ustk & 0x1ff) == 0x1f8)