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Various whitespace and style fixes.

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This commit is contained in:
John Baldwin 2006-11-15 19:53:48 +00:00
parent 28c75f229d
commit 71f4007710
6 changed files with 86 additions and 88 deletions
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71
sys/amd64/amd64/db_trace.c
View File

@ -202,8 +202,8 @@ static void decode_syscall(int, struct thread *);
static char * watchtype_str(int type); static char * watchtype_str(int type);
int amd64_set_watch(int watchnum, unsigned long watchaddr, int size, int amd64_set_watch(int watchnum, unsigned long watchaddr, int size,
int access, struct dbreg * d); int access, struct dbreg *d);
int amd64_clr_watch(int watchnum, struct dbreg * d); int amd64_clr_watch(int watchnum, struct dbreg *d);
/* /*
* Figure out how many arguments were passed into the frame at "fp". * Figure out how many arguments were passed into the frame at "fp".
@ -536,11 +536,11 @@ amd64_set_watch(watchnum, watchaddr, size, access, d)
unsigned long watchaddr; unsigned long watchaddr;
int size; int size;
int access; int access;
struct dbreg * d; struct dbreg *d;
{ {
int i; int i;
unsigned int mask; unsigned int mask;
if (watchnum == -1) { if (watchnum == -1) {
for (i = 0, mask = 0x3; i < 4; i++, mask <<= 2) for (i = 0, mask = 0x3; i < 4; i++, mask <<= 2)
if ((d->dr[7] & mask) == 0) if ((d->dr[7] & mask) == 0)
@ -550,7 +550,7 @@ amd64_set_watch(watchnum, watchaddr, size, access, d)
else else
return (-1); return (-1);
} }
switch (access) { switch (access) {
case DBREG_DR7_EXEC: case DBREG_DR7_EXEC:
size = 1; /* size must be 1 for an execution breakpoint */ size = 1; /* size must be 1 for an execution breakpoint */
@ -558,9 +558,10 @@ amd64_set_watch(watchnum, watchaddr, size, access, d)
case DBREG_DR7_WRONLY: case DBREG_DR7_WRONLY:
case DBREG_DR7_RDWR: case DBREG_DR7_RDWR:
break; break;
default : return (-1); default:
return (-1);
} }
/* /*
* we can watch a 1, 2, or 4 byte sized location * we can watch a 1, 2, or 4 byte sized location
*/ */
@ -577,7 +578,7 @@ amd64_set_watch(watchnum, watchaddr, size, access, d)
d->dr[7] &= ~((0x3 << (watchnum*2)) | (0x0f << (watchnum*4+16))); d->dr[7] &= ~((0x3 << (watchnum*2)) | (0x0f << (watchnum*4+16)));
/* set drN register to the address, N=watchnum */ /* set drN register to the address, N=watchnum */
DBREG_DRX(d,watchnum) = watchaddr; DBREG_DRX(d, watchnum) = watchaddr;
/* enable the watchpoint */ /* enable the watchpoint */
d->dr[7] |= (0x2 << (watchnum*2)) | (mask << (watchnum*4+16)); d->dr[7] |= (0x2 << (watchnum*2)) | (mask << (watchnum*4+16));
@ -589,15 +590,15 @@ amd64_set_watch(watchnum, watchaddr, size, access, d)
int int
amd64_clr_watch(watchnum, d) amd64_clr_watch(watchnum, d)
int watchnum; int watchnum;
struct dbreg * d; struct dbreg *d;
{ {
if (watchnum < 0 || watchnum >= 4) if (watchnum < 0 || watchnum >= 4)
return (-1); return (-1);
d->dr[7] = d->dr[7] & ~((0x3 << (watchnum*2)) | (0x0f << (watchnum*4+16))); d->dr[7] = d->dr[7] & ~((0x3 << (watchnum*2)) | (0x0f << (watchnum*4+16)));
DBREG_DRX(d,watchnum) = 0; DBREG_DRX(d, watchnum) = 0;
return (0); return (0);
} }
@ -607,22 +608,21 @@ db_md_set_watchpoint(addr, size)
db_expr_t addr; db_expr_t addr;
db_expr_t size; db_expr_t size;
{ {
int avail, wsize;
int i;
struct dbreg d; struct dbreg d;
int avail, i, wsize;
fill_dbregs(NULL, &d); fill_dbregs(NULL, &d);
avail = 0; avail = 0;
for(i=0; i<4; i++) { for(i = 0; i < 4; i++) {
if ((d.dr[7] & (3 << (i*2))) == 0) if ((d.dr[7] & (3 << (i*2))) == 0)
avail++; avail++;
} }
if (avail*4 < size) if (avail * 4 < size)
return (-1); return (-1);
for (i=0; i<4 && (size != 0); i++) { for (i = 0; i < 4 && (size != 0); i++) {
if ((d.dr[7] & (3<<(i*2))) == 0) { if ((d.dr[7] & (3<<(i*2))) == 0) {
if (size > 4) if (size > 4)
wsize = 4; wsize = 4;
@ -630,15 +630,15 @@ db_md_set_watchpoint(addr, size)
wsize = size; wsize = size;
if (wsize == 3) if (wsize == 3)
wsize++; wsize++;
amd64_set_watch(i, addr, wsize, amd64_set_watch(i, addr, wsize,
DBREG_DR7_WRONLY, &d); DBREG_DR7_WRONLY, &d);
addr += wsize; addr += wsize;
size -= wsize; size -= wsize;
} }
} }
set_dbregs(NULL, &d); set_dbregs(NULL, &d);
return(0); return(0);
} }
@ -653,22 +653,22 @@ db_md_clr_watchpoint(addr, size)
fill_dbregs(NULL, &d); fill_dbregs(NULL, &d);
for(i=0; i<4; i++) { for(i = 0; i < 4; i++) {
if (d.dr[7] & (3 << (i*2))) { if (d.dr[7] & (3 << (i*2))) {
if ((DBREG_DRX((&d), i) >= addr) && if ((DBREG_DRX((&d), i) >= addr) &&
(DBREG_DRX((&d), i) < addr+size)) (DBREG_DRX((&d), i) < addr+size))
amd64_clr_watch(i, &d); amd64_clr_watch(i, &d);
} }
} }
set_dbregs(NULL, &d); set_dbregs(NULL, &d);
return(0); return(0);
} }
static static
char * char *
watchtype_str(type) watchtype_str(type)
int type; int type;
@ -685,30 +685,29 @@ watchtype_str(type)
void void
db_md_list_watchpoints() db_md_list_watchpoints()
{ {
int i;
struct dbreg d; struct dbreg d;
int i, len, type;
fill_dbregs(NULL, &d); fill_dbregs(NULL, &d);
db_printf("\nhardware watchpoints:\n"); db_printf("\nhardware watchpoints:\n");
db_printf(" watch status type len address\n"); db_printf(" watch status type len address\n");
db_printf(" ----- -------- ---------- --- ----------\n"); db_printf(" ----- -------- ---------- --- ----------\n");
for (i=0; i<4; i++) { for (i = 0; i < 4; i++) {
if (d.dr[7] & (0x03 << (i*2))) { if (d.dr[7] & (0x03 << (i*2))) {
unsigned type, len;
type = (d.dr[7] >> (16+(i*4))) & 3; type = (d.dr[7] >> (16+(i*4))) & 3;
len = (d.dr[7] >> (16+(i*4)+2)) & 3; len = (d.dr[7] >> (16+(i*4)+2)) & 3;
db_printf(" %-5d %-8s %10s %3d 0x%016lx\n", db_printf(" %-5d %-8s %10s %3d 0x%016lx\n",
i, "enabled", watchtype_str(type), i, "enabled", watchtype_str(type),
len + 1, DBREG_DRX((&d), i)); len + 1, DBREG_DRX((&d), i));
} }
else { else {
db_printf(" %-5d disabled\n", i); db_printf(" %-5d disabled\n", i);
} }
} }
db_printf("\ndebug register values:\n"); db_printf("\ndebug register values:\n");
for (i=0; i<8; i++) { for (i = 0; i < 8; i++) {
db_printf(" dr%d 0x%016lx\n", i, DBREG_DRX((&d), i)); db_printf(" dr%d 0x%016lx\n", i, DBREG_DRX((&d), i));
} }
db_printf("\n"); db_printf("\n");

5
sys/amd64/amd64/machdep.c
View File

@ -1832,9 +1832,8 @@ user_dbreg_trap(void)
addr[nbp++] = (caddr_t)rdr3(); addr[nbp++] = (caddr_t)rdr3();
} }
for (i=0; i<nbp; i++) { for (i = 0; i < nbp; i++) {
if (addr[i] < if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) {
(caddr_t)VM_MAXUSER_ADDRESS) {
/* /*
* addr[i] is in user space * addr[i] is in user space
*/ */

12
sys/amd64/include/reg.h
View File

@ -92,11 +92,13 @@ struct dbreg {
/* Index 8-15: reserved */ /* Index 8-15: reserved */
}; };
#define DBREG_DR7_EXEC 0x00 /* break on execute */ #define DBREG_DR7_EXEC 0x00 /* break on execute */
#define DBREG_DR7_WRONLY 0x01 /* break on write */ #define DBREG_DR7_WRONLY 0x01 /* break on write */
#define DBREG_DR7_RDWR 0x03 /* break on read or write */ #define DBREG_DR7_RDWR 0x03 /* break on read or write */
#define DBREG_DRX(d,x) ((d)->dr[(x)]) /* reference dr0 - dr15 by
register number */ #define DBREG_DRX(d,x) ((d)->dr[(x)]) /* reference dr0 - dr15 by
register number */
#ifdef _KERNEL #ifdef _KERNEL
/* /*
* XXX these interfaces are MI, so they should be declared in a MI place. * XXX these interfaces are MI, so they should be declared in a MI place.

71
sys/i386/i386/db_trace.c
View File

@ -192,8 +192,8 @@ static void decode_syscall(int, struct thread *);
static char * watchtype_str(int type); static char * watchtype_str(int type);
int i386_set_watch(int watchnum, unsigned int watchaddr, int size, int access, int i386_set_watch(int watchnum, unsigned int watchaddr, int size, int access,
struct dbreg * d); struct dbreg *d);
int i386_clr_watch(int watchnum, struct dbreg * d); int i386_clr_watch(int watchnum, struct dbreg *d);
/* /*
* Figure out how many arguments were passed into the frame at "fp". * Figure out how many arguments were passed into the frame at "fp".
@ -569,11 +569,11 @@ i386_set_watch(watchnum, watchaddr, size, access, d)
unsigned int watchaddr; unsigned int watchaddr;
int size; int size;
int access; int access;
struct dbreg * d; struct dbreg *d;
{ {
int i; int i;
unsigned int mask; unsigned int mask;
if (watchnum == -1) { if (watchnum == -1) {
for (i = 0, mask = 0x3; i < 4; i++, mask <<= 2) for (i = 0, mask = 0x3; i < 4; i++, mask <<= 2)
if ((d->dr[7] & mask) == 0) if ((d->dr[7] & mask) == 0)
@ -583,7 +583,7 @@ i386_set_watch(watchnum, watchaddr, size, access, d)
else else
return (-1); return (-1);
} }
switch (access) { switch (access) {
case DBREG_DR7_EXEC: case DBREG_DR7_EXEC:
size = 1; /* size must be 1 for an execution breakpoint */ size = 1; /* size must be 1 for an execution breakpoint */
@ -591,9 +591,10 @@ i386_set_watch(watchnum, watchaddr, size, access, d)
case DBREG_DR7_WRONLY: case DBREG_DR7_WRONLY:
case DBREG_DR7_RDWR: case DBREG_DR7_RDWR:
break; break;
default : return (-1); default:
return (-1);
} }
/* /*
* we can watch a 1, 2, or 4 byte sized location * we can watch a 1, 2, or 4 byte sized location
*/ */
@ -610,7 +611,7 @@ i386_set_watch(watchnum, watchaddr, size, access, d)
d->dr[7] &= ~((0x3 << (watchnum*2)) | (0x0f << (watchnum*4+16))); d->dr[7] &= ~((0x3 << (watchnum*2)) | (0x0f << (watchnum*4+16)));
/* set drN register to the address, N=watchnum */ /* set drN register to the address, N=watchnum */
DBREG_DRX(d,watchnum) = watchaddr; DBREG_DRX(d, watchnum) = watchaddr;
/* enable the watchpoint */ /* enable the watchpoint */
d->dr[7] |= (0x2 << (watchnum*2)) | (mask << (watchnum*4+16)); d->dr[7] |= (0x2 << (watchnum*2)) | (mask << (watchnum*4+16));
@ -622,15 +623,15 @@ i386_set_watch(watchnum, watchaddr, size, access, d)
int int
i386_clr_watch(watchnum, d) i386_clr_watch(watchnum, d)
int watchnum; int watchnum;
struct dbreg * d; struct dbreg *d;
{ {
if (watchnum < 0 || watchnum >= 4) if (watchnum < 0 || watchnum >= 4)
return (-1); return (-1);
d->dr[7] = d->dr[7] & ~((0x3 << (watchnum*2)) | (0x0f << (watchnum*4+16))); d->dr[7] = d->dr[7] & ~((0x3 << (watchnum*2)) | (0x0f << (watchnum*4+16)));
DBREG_DRX(d,watchnum) = 0; DBREG_DRX(d, watchnum) = 0;
return (0); return (0);
} }
@ -640,22 +641,21 @@ db_md_set_watchpoint(addr, size)
db_expr_t addr; db_expr_t addr;
db_expr_t size; db_expr_t size;
{ {
int avail, wsize;
int i;
struct dbreg d; struct dbreg d;
int avail, i, wsize;
fill_dbregs(NULL, &d); fill_dbregs(NULL, &d);
avail = 0; avail = 0;
for(i=0; i<4; i++) { for(i = 0; i < 4; i++) {
if ((d.dr[7] & (3 << (i*2))) == 0) if ((d.dr[7] & (3 << (i*2))) == 0)
avail++; avail++;
} }
if (avail*4 < size) if (avail * 4 < size)
return (-1); return (-1);
for (i=0; i<4 && (size != 0); i++) { for (i = 0; i < 4 && (size != 0); i++) {
if ((d.dr[7] & (3<<(i*2))) == 0) { if ((d.dr[7] & (3<<(i*2))) == 0) {
if (size > 4) if (size > 4)
wsize = 4; wsize = 4;
@ -663,15 +663,15 @@ db_md_set_watchpoint(addr, size)
wsize = size; wsize = size;
if (wsize == 3) if (wsize == 3)
wsize++; wsize++;
i386_set_watch(i, addr, wsize, i386_set_watch(i, addr, wsize,
DBREG_DR7_WRONLY, &d); DBREG_DR7_WRONLY, &d);
addr += wsize; addr += wsize;
size -= wsize; size -= wsize;
} }
} }
set_dbregs(NULL, &d); set_dbregs(NULL, &d);
return(0); return(0);
} }
@ -686,22 +686,22 @@ db_md_clr_watchpoint(addr, size)
fill_dbregs(NULL, &d); fill_dbregs(NULL, &d);
for(i=0; i<4; i++) { for(i = 0; i < 4; i++) {
if (d.dr[7] & (3 << (i*2))) { if (d.dr[7] & (3 << (i*2))) {
if ((DBREG_DRX((&d), i) >= addr) && if ((DBREG_DRX((&d), i) >= addr) &&
(DBREG_DRX((&d), i) < addr+size)) (DBREG_DRX((&d), i) < addr+size))
i386_clr_watch(i, &d); i386_clr_watch(i, &d);
} }
} }
set_dbregs(NULL, &d); set_dbregs(NULL, &d);
return(0); return(0);
} }
static static
char * char *
watchtype_str(type) watchtype_str(type)
int type; int type;
@ -718,30 +718,29 @@ watchtype_str(type)
void void
db_md_list_watchpoints() db_md_list_watchpoints()
{ {
int i;
struct dbreg d; struct dbreg d;
int i, len, type;
fill_dbregs(NULL, &d); fill_dbregs(NULL, &d);
db_printf("\nhardware watchpoints:\n"); db_printf("\nhardware watchpoints:\n");
db_printf(" watch status type len address\n"); db_printf(" watch status type len address\n");
db_printf(" ----- -------- ---------- --- ----------\n"); db_printf(" ----- -------- ---------- --- ----------\n");
for (i=0; i<4; i++) { for (i = 0; i < 4; i++) {
if (d.dr[7] & (0x03 << (i*2))) { if (d.dr[7] & (0x03 << (i*2))) {
unsigned type, len;
type = (d.dr[7] >> (16+(i*4))) & 3; type = (d.dr[7] >> (16+(i*4))) & 3;
len = (d.dr[7] >> (16+(i*4)+2)) & 3; len = (d.dr[7] >> (16+(i*4)+2)) & 3;
db_printf(" %-5d %-8s %10s %3d 0x%08x\n", db_printf(" %-5d %-8s %10s %3d 0x%08x\n",
i, "enabled", watchtype_str(type), i, "enabled", watchtype_str(type),
len+1, DBREG_DRX((&d),i)); len+1, DBREG_DRX((&d),i));
} }
else { else {
db_printf(" %-5d disabled\n", i); db_printf(" %-5d disabled\n", i);
} }
} }
db_printf("\ndebug register values:\n"); db_printf("\ndebug register values:\n");
for (i=0; i<8; i++) { for (i = 0; i < 8; i++) {
db_printf(" dr%d 0x%08x\n", i, DBREG_DRX((&d),i)); db_printf(" dr%d 0x%08x\n", i, DBREG_DRX((&d),i));
} }
db_printf("\n"); db_printf("\n");

5
sys/i386/i386/machdep.c
View File

@ -2904,9 +2904,8 @@ user_dbreg_trap(void)
addr[nbp++] = (caddr_t)rdr3(); addr[nbp++] = (caddr_t)rdr3();
} }
for (i=0; i<nbp; i++) { for (i = 0; i < nbp; i++) {
if (addr[i] < if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) {
(caddr_t)VM_MAXUSER_ADDRESS) {
/* /*
* addr[i] is in user space * addr[i] is in user space
*/ */

10
sys/i386/include/reg.h
View File

@ -137,12 +137,12 @@ struct dbreg {
/* Index 7: debug control */ /* Index 7: debug control */
}; };
#define DBREG_DR7_EXEC 0x00 /* break on execute */ #define DBREG_DR7_EXEC 0x00 /* break on execute */
#define DBREG_DR7_WRONLY 0x01 /* break on write */ #define DBREG_DR7_WRONLY 0x01 /* break on write */
#define DBREG_DR7_RDWR 0x03 /* break on read or write */ #define DBREG_DR7_RDWR 0x03 /* break on read or write */
#define DBREG_DRX(d,x) ((d)->dr[(x)]) /* reference dr0 - dr7 by
register number */
#define DBREG_DRX(d,x) ((d)->dr[(x)]) /* reference dr0 - dr7 by
register number */
#ifdef _KERNEL #ifdef _KERNEL
/* /*