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Rework DL10019/DL10022 support. This tries to reset things in a more

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proper way, or at least the same way that NetBSD and Linux do things
(I've been unable to obtain datasheets for these parts to know for
sure).  This has some marginal improvement in the DL10022 and DL10019
cards that I have.  Also, report which type, exactly.

# There's one or two ed cards that I have which still don't work, but I think
# that's due to MII losage on the card that's not presently compensated
# for in the MII drivers.
This commit is contained in:
imp 2005-02-14 06:54:06 +00:00
parent 9392069e8f
commit 72c4151f9c
2 changed files with 29 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
sys/dev/ed/if_ed_pccard.c
View File

@ -308,7 +308,8 @@ ed_pccard_attach(device_t dev)
error = ed_attach(dev); error = ed_attach(dev);
#ifndef ED_NO_MIIBUS #ifndef ED_NO_MIIBUS
if (error == 0 && sc->chip_type == ED_CHIP_TYPE_DL100XX) { if (error == 0 && (sc->chip_type == ED_CHIP_TYPE_DL10019 ||
sc->chip_type == ED_CHIP_TYPE_DL10022)) {
/* Probe for an MII bus, but ignore errors. */ /* Probe for an MII bus, but ignore errors. */
ed_pccard_dlink_mii_reset(sc); ed_pccard_dlink_mii_reset(sc);
sc->mii_readbits = ed_pccard_dlink_mii_readbits; sc->mii_readbits = ed_pccard_dlink_mii_readbits;
@ -445,7 +446,8 @@ ed_pccard_Linksys(device_t dev)
sc->isa16bit = 1; sc->isa16bit = 1;
sc->vendor = ED_VENDOR_NOVELL; sc->vendor = ED_VENDOR_NOVELL;
sc->type = ED_TYPE_NE2000; sc->type = ED_TYPE_NE2000;
sc->chip_type = ED_CHIP_TYPE_DL100XX; sc->chip_type = (id & 0x90) == 0x90 ?
ED_CHIP_TYPE_DL10022 : ED_CHIP_TYPE_DL10019;
sc->type_str = ((id & 0x90) == 0x90) ? "DL10022" : "DL10019"; sc->type_str = ((id & 0x90) == 0x90) ? "DL10022" : "DL10019";
return (0); return (0);
} }
@ -503,16 +505,20 @@ static void
ed_pccard_dlink_mii_reset(sc) ed_pccard_dlink_mii_reset(sc)
struct ed_softc *sc; struct ed_softc *sc;
{ {
if (sc->chip_type != ED_CHIP_TYPE_DL10022)
return;
ed_asic_outb(sc, ED_DLINK_MIIBUS, ED_DLINK_MII_RESET2);
DELAY(10);
ed_asic_outb(sc, ED_DLINK_MIIBUS,
ED_DLINK_MII_RESET2 | ED_DLINK_MII_RESET1);
DELAY(10);
ed_asic_outb(sc, ED_DLINK_MIIBUS, ED_DLINK_MII_RESET2);
DELAY(10);
ed_asic_outb(sc, ED_DLINK_MIIBUS,
ED_DLINK_MII_RESET2 | ED_DLINK_MII_RESET1);
DELAY(10);
ed_asic_outb(sc, ED_DLINK_MIIBUS, 0); ed_asic_outb(sc, ED_DLINK_MIIBUS, 0);
DELAY(10);
DLINK_MIISET(sc, ED_DLINK_MII_RESET2);
DELAY(10);
DLINK_MIISET(sc, ED_DLINK_MII_RESET1);
DELAY(10);
DLINK_MIICLR(sc, ED_DLINK_MII_RESET1);
DELAY(10);
DLINK_MIICLR(sc, ED_DLINK_MII_RESET2);
DELAY(10);
} }
static void static void
@ -523,7 +529,10 @@ ed_pccard_dlink_mii_writebits(sc, val, nbits)
{ {
int i; int i;
DLINK_MIISET(sc, ED_DLINK_MII_DIROUT); if (sc->chip_type == ED_CHIP_TYPE_DL10022)
DLINK_MIISET(sc, ED_DLINK_MII_DIROUT_22);
else
DLINK_MIISET(sc, ED_DLINK_MII_DIROUT_19);
for (i = nbits - 1; i >= 0; i--) { for (i = nbits - 1; i >= 0; i--) {
if ((val >> i) & 1) if ((val >> i) & 1)
@ -546,7 +555,10 @@ ed_pccard_dlink_mii_readbits(sc, nbits)
int i; int i;
u_int val = 0; u_int val = 0;
DLINK_MIICLR(sc, ED_DLINK_MII_DIROUT); if (sc->chip_type == ED_CHIP_TYPE_DL10022)
DLINK_MIICLR(sc, ED_DLINK_MII_DIROUT_22);
else
DLINK_MIICLR(sc, ED_DLINK_MII_DIROUT_19);
for (i = nbits - 1; i >= 0; i--) { for (i = nbits - 1; i >= 0; i--) {
DLINK_MIISET(sc, ED_DLINK_MII_CLK); DLINK_MIISET(sc, ED_DLINK_MII_CLK);

6
sys/dev/ed/if_edreg.h
View File

@ -1114,7 +1114,8 @@ struct ed_ring {
#define ED_CHIP_TYPE_DP8390 0x00 #define ED_CHIP_TYPE_DP8390 0x00
#define ED_CHIP_TYPE_WD790 0x01 #define ED_CHIP_TYPE_WD790 0x01
#define ED_CHIP_TYPE_AX88190 0x02 #define ED_CHIP_TYPE_AX88190 0x02
#define ED_CHIP_TYPE_DL100XX 0x03 #define ED_CHIP_TYPE_DL10019 0x03
#define ED_CHIP_TYPE_DL10022 0x04
/* /*
* AX88190 configuration status register. * AX88190 configuration status register.
@ -1158,6 +1159,7 @@ struct ed_ring {
#define ED_DLINK_MII_RESET2 0x08 #define ED_DLINK_MII_RESET2 0x08
#define ED_DLINK_MII_DATATIN 0x10 #define ED_DLINK_MII_DATATIN 0x10
#define ED_DLINK_MII_DIROUT 0x20 #define ED_DLINK_MII_DIROUT_22 0x20
#define ED_DLINK_MII_DIROUT_19 0x10
#define ED_DLINK_MII_DATAOUT 0x40 #define ED_DLINK_MII_DATAOUT 0x40
#define ED_DLINK_MII_CLK 0x80 #define ED_DLINK_MII_CLK 0x80