Hide most of the PTE initialization and management.
By confining the page table management to a handful of functions it'll be easier to modify the page table scheme without affecting other functions. This will be necessary when 64-bit support is added, and page tables become much larger.
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jhibbits
parent
09fb369fc5
commit
730341be8a
@ -242,6 +242,8 @@ static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t);
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static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t);
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static int pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t);
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static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t);
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static void kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr,
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vm_offset_t pdir);
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static pv_entry_t pv_alloc(void);
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static void pv_free(pv_entry_t);
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@ -507,6 +509,10 @@ tlb1_get_tlbconf(void)
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tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK;
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}
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/**************************************************************************/
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/* Page table related */
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/**************************************************************************/
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/* Initialize pool of kva ptbl buffers. */
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static void
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ptbl_init(void)
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@ -1014,6 +1020,33 @@ pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va)
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return (NULL);
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}
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/* Set up kernel page tables. */
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static void
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kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir)
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{
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int i;
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vm_offset_t va;
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pte_t *pte;
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/* Initialize kernel pdir */
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for (i = 0; i < kernel_ptbls; i++)
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kernel_pmap->pm_pdir[kptbl_min + i] =
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(pte_t *)(pdir + (i * PAGE_SIZE * PTBL_PAGES));
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/*
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* Fill in PTEs covering kernel code and data. They are not required
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* for address translation, as this area is covered by static TLB1
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* entries, but for pte_vatopa() to work correctly with kernel area
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* addresses.
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*/
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for (va = addr; va < data_end; va += PAGE_SIZE) {
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pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]);
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pte->rpn = kernload + (va - kernstart);
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pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
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PTE_VALID;
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}
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}
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/**************************************************************************/
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/* PMAP related */
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/**************************************************************************/
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@ -1031,10 +1064,9 @@ mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend)
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vm_paddr_t physsz, hwphyssz;
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u_int phys_avail_count;
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vm_size_t kstack0_sz;
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vm_offset_t kernel_pdir, kstack0, va;
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vm_offset_t kernel_pdir, kstack0;
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vm_paddr_t kstack0_phys;
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void *dpcpu;
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pte_t *pte;
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debugf("mmu_booke_bootstrap: entered\n");
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@ -1287,11 +1319,7 @@ mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend)
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debugf("kernel pdir range: 0x%08x - 0x%08x\n",
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kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1);
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/* Initialize kernel pdir */
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for (i = 0; i < kernel_ptbls; i++)
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kernel_pmap->pm_pdir[kptbl_min + i] =
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(pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES));
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kernel_pte_alloc(data_end, kernstart, kernel_pdir);
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for (i = 0; i < MAXCPU; i++) {
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kernel_pmap->pm_tid[i] = TID_KERNEL;
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@ -1299,18 +1327,6 @@ mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend)
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tidbusy[i][TID_KERNEL] = kernel_pmap;
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}
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/*
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* Fill in PTEs covering kernel code and data. They are not required
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* for address translation, as this area is covered by static TLB1
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* entries, but for pte_vatopa() to work correctly with kernel area
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* addresses.
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*/
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for (va = kernstart; va < data_end; va += PAGE_SIZE) {
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pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]);
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pte->rpn = kernload + (va - kernstart);
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pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
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PTE_VALID;
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}
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/* Mark kernel_pmap active on all CPUs */
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CPU_FILL(&kernel_pmap->pm_active);
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@ -1502,8 +1518,6 @@ mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
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static void
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mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
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{
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unsigned int pdir_idx = PDIR_IDX(va);
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unsigned int ptbl_idx = PTBL_IDX(va);
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uint32_t flags;
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pte_t *pte;
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@ -1513,7 +1527,7 @@ mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
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flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
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flags |= tlb_calc_wimg(pa, ma);
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pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
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pte = pte_find(mmu, kernel_pmap, va);
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mtx_lock_spin(&tlbivax_mutex);
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tlb_miss_lock();
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@ -1548,17 +1562,15 @@ mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
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static void
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mmu_booke_kremove(mmu_t mmu, vm_offset_t va)
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{
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unsigned int pdir_idx = PDIR_IDX(va);
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unsigned int ptbl_idx = PTBL_IDX(va);
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pte_t *pte;
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// CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va));
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CTR2(KTR_PMAP,"%s: s (va = 0x%08x)\n", __func__, va);
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KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
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(va <= VM_MAX_KERNEL_ADDRESS)),
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("mmu_booke_kremove: invalid va"));
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pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
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pte = pte_find(mmu, kernel_pmap, va);
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if (!PTE_ISVALID(pte)) {
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@ -2333,7 +2345,7 @@ mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m)
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critical_enter();
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qaddr = PCPU_GET(qmap_addr);
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pte = &(kernel_pmap->pm_pdir[PDIR_IDX(qaddr)][PTBL_IDX(qaddr)]);
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pte = pte_find(mmu, kernel_pmap, qaddr);
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KASSERT(pte->flags == 0, ("mmu_booke_quick_enter_page: PTE busy"));
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@ -2360,7 +2372,7 @@ mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr)
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{
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pte_t *pte;
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pte = &(kernel_pmap->pm_pdir[PDIR_IDX(addr)][PTBL_IDX(addr)]);
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pte = pte_find(mmu, kernel_pmap, addr);
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KASSERT(PCPU_GET(qmap_addr) == addr,
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("mmu_booke_quick_remove_page: invalid address"));
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@ -2832,8 +2844,8 @@ mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
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} while (va % sz != 0);
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}
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if (bootverbose)
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printf("Wiring VA=%x to PA=%llx (size=%x), "
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"using TLB1[%d]\n", va, pa, sz, tlb1_idx);
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printf("Wiring VA=%lx to PA=%jx (size=%lx), "
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"using TLB1[%d]\n", va, (uintmax_t)pa, sz, tlb1_idx);
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tlb1_set_entry(va, pa, sz, tlb_calc_wimg(pa, ma));
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size -= sz;
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pa += sz;
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@ -3237,7 +3249,11 @@ tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
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}
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mapped = (va - base);
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#ifdef __powerpc64__
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printf("mapped size 0x%016lx (wasted space 0x%16lx)\n",
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#else
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printf("mapped size 0x%08x (wasted space 0x%08x)\n",
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#endif
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mapped, mapped - size);
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return (mapped);
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}
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