Remove trailing whitespace.
This commit is contained in:
joel
parent
8d728b03ba
commit
74011e5f91
@ -442,147 +442,147 @@ Set Cmask = 1 to count cycles.
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.It Li PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW
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.Pq Event 59H , Umask 0FH
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Cycles with at least one slow LEA uop allocated.
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.It Li PARTIAL_RAT_STALLS.MUL_SINGLE_UOP
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.It Li PARTIAL_RAT_STALLS.MUL_SINGLE_UOP
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.Pq Event 59H , Umask 40H
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Number of Multiply packed/scalar single precision
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uops allocated.
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.It Li RESOURCE_STALLS2.ALL_FL_EMPTY
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.It Li RESOURCE_STALLS2.ALL_FL_EMPTY
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.Pq Event 5BH , Umask 0CH
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Cycles stalled due to free list empty.
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.It Li RESOURCE_STALLS2.ALL_PRF_CONTROL
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Cycles stalled due to free list empty.
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.It Li RESOURCE_STALLS2.ALL_PRF_CONTROL
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.Pq Event 5BH , Umask 0FH
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Cycles stalled due to control structures full for
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physical registers.
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.It Li RESOURCE_STALLS2.BOB_FULL
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.It Li RESOURCE_STALLS2.BOB_FULL
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.Pq Event 5BH , Umask 40H
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Cycles Allocator is stalled due Branch Order Buffer.
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.It Li RESOURCE_STALLS2.OOO_RSRC
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Cycles Allocator is stalled due Branch Order Buffer.
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.It Li RESOURCE_STALLS2.OOO_RSRC
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.Pq Event 5BH , Umask 4FH
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Cycles stalled due to out of order resources full.
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.It Li CPL_CYCLES.RING0
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Cycles stalled due to out of order resources full.
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.It Li CPL_CYCLES.RING0
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.Pq Event 5CH , Umask 01H
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Unhalted core cycles when the thread is in ring 0.
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.It Li CPL_CYCLES.RING123
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Unhalted core cycles when the thread is in ring 0.
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.It Li CPL_CYCLES.RING123
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.Pq Event 5CH , Umask 02H
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Unhalted core cycles when the thread is not in ring
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0.
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.It Li RS_EVENTS.EMPTY_CYCLES
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.Pq Event 5EH , Umask 01H
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Cycles the RS is empty for the thread.
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.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
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Cycles the RS is empty for the thread.
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.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
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.Pq Event 60H , Umask 01H
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Offcore outstanding Demand Data Read
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transactions in SQ to uncore. Set Cmask=1 to count
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cycles.
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.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
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.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
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.Pq Event 60H , Umask 04H
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Offcore outstanding RFO store transactions in SQ to
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uncore. Set Cmask=1 to count cycles.
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.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
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.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
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.Pq Event 60H , Umask 08H
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Offcore outstanding cacheable data read
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transactions in SQ to uncore. Set Cmask=1 to count
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cycles.
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.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION
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.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION
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.Pq Event 63H , Umask 01H
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Cycles in which the L1D and L2 are locked, due to a
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UC lock or split lock.
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.It Li LOCK_CYCLES.CACHE_LOCK_DURATION
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.It Li LOCK_CYCLES.CACHE_LOCK_DURATION
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.Pq Event 63H , Umask 02H
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Cycles in which the L1D is locked.
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.It Li IDQ.EMPTY
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Cycles in which the L1D is locked.
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.It Li IDQ.EMPTY
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.Pq Event 79H , Umask 02H
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Counts cycles the IDQ is empty.
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.It Li IDQ.MITE_UOPS
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.It Li IDQ.MITE_UOPS
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.Pq Event 79H , Umask 04H
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Increment each cycle # of uops delivered to IDQ
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from MITE path.
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Set Cmask = 1 to count cycles.
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.It Li IDQ.DSB_UOPS
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.It Li IDQ.DSB_UOPS
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.Pq Event 79H , Umask 08H
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Increment each cycle. # of uops delivered to IDQ
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from DSB path.
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Set Cmask = 1 to count cycles.
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.It Li IDQ.MS_DSB_UOPS
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.It Li IDQ.MS_DSB_UOPS
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.Pq Event 79H , Umask 10H
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Increment each cycle # of uops delivered to IDQ
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when MS busy by DSB. Set Cmask = 1 to count
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cycles MS is busy. Set Cmask=1 and Edge =1 to
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count MS activations.
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.It Li IDQ.MS_MITE_UOPS
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.It Li IDQ.MS_MITE_UOPS
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.Pq Event 79H , Umask 20H
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Increment each cycle # of uops delivered to IDQ
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when MS is busy by MITE. Set Cmask = 1 to count
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cycles.
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.It Li IDQ.MS_UOPS
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.It Li IDQ.MS_UOPS
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.Pq Event 79H , Umask 30H
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Increment each cycle # of uops delivered to IDQ
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from MS by either DSB or MITE. Set Cmask = 1 to
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count cycles.
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.It Li ICACHE.MISSES
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.It Li ICACHE.MISSES
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.Pq Event 80H , Umask 02H
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Number of Instruction Cache, Streaming Buffer and
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Victim Cache Misses. Includes UC accesses.
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.It Li ITLB_MISSES.MISS_CAUSES_A_WALK
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.It Li ITLB_MISSES.MISS_CAUSES_A_WALK
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.Pq Event 85H , Umask 01H
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Misses in all ITLB levels that cause page walks.
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.It Li ITLB_MISSES.WALK_COMPLETED
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Misses in all ITLB levels that cause page walks.
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.It Li ITLB_MISSES.WALK_COMPLETED
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.Pq Event 85H , Umask 02H
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Misses in all ITLB levels that cause completed page
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walks.
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.It Li ITLB_MISSES.WALK_DURATION
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.It Li ITLB_MISSES.WALK_DURATION
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.Pq Event 85H , Umask 04H
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Cycle PMH is busy with a walk.
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.It Li ITLB_MISSES.STLB_HIT
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Cycle PMH is busy with a walk.
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.It Li ITLB_MISSES.STLB_HIT
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.Pq Event 85H , Umask 10H
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Number of cache load STLB hits. No page walk.
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.It Li ILD_STALL.LCP
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Number of cache load STLB hits. No page walk.
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.It Li ILD_STALL.LCP
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.Pq Event 87H , Umask 01H
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Stalls caused by changing prefix length of the
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instruction.
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.It Li ILD_STALL.IQ_FULL
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.It Li ILD_STALL.IQ_FULL
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.Pq Event 87H , Umask 04H
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Stall cycles due to IQ is full.
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Stall cycles due to IQ is full.
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.It Li BR_INST_EXEC.COND
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.Pq Event 88H , Umask 01H
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Qualify conditional near branch instructions
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executed, but not necessarily retired.
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.It Li BR_INST_EXEC.DIRECT_JMP
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.It Li BR_INST_EXEC.DIRECT_JMP
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.Pq Event 88H , Umask 02H
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Qualify all unconditional near branch instructions
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excluding calls and indirect branches.
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.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
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.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
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.Pq Event 88H , Umask 04H
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Qualify executed indirect near branch instructions
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that are not calls nor returns.
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.It Li BR_INST_EXEC.RETURN_NEAR
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.It Li BR_INST_EXEC.RETURN_NEAR
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.Pq Event 88H , Umask 08H
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Qualify indirect near branches that have a return
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mnemonic.
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.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
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.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
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.Pq Event 88H , Umask 10H
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Qualify unconditional near call branch instructions,
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excluding non call branch, executed.
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.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
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.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
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.Pq Event 88H , Umask 20H
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Qualify indirect near calls, including both register
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and memory indirect, executed.
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.It Li BR_INST_EXEC.NONTAKEN
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.It Li BR_INST_EXEC.NONTAKEN
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.Pq Event 88H , Umask 40H
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Qualify non-taken near branches executed.
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.It Li BR_INST_EXEC.TAKEN
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Qualify non-taken near branches executed.
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.It Li BR_INST_EXEC.TAKEN
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.Pq Event 88H , Umask 80H
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Qualify taken near branches executed. Must
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combine with 01H,02H, 04H, 08H, 10H, 20H.
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.It Li BR_INST_EXE.ALL_BRANCHES
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.It Li BR_INST_EXE.ALL_BRANCHES
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.Pq Event 88H , Umask FFH
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Counts all near executed branches (not necessarily
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retired).
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.It Li BR_MISP_EXEC.COND
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.It Li BR_MISP_EXEC.COND
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.Pq Event 89H , Umask 01H
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Qualify conditional near branch instructions
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mispredicted.
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.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
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.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
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.Pq Event 89H , Umask 04H
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Qualify mispredicted indirect near branch
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instructions that are not calls nor returns.
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@ -590,144 +590,144 @@ instructions that are not calls nor returns.
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.Pq Event 89H , Umask 08H
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Qualify mispredicted indirect near branches that
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have a return mnemonic.
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.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
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.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
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.Pq Event 89H , Umask 10H
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Qualify mispredicted unconditional near call branch
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instructions, excluding non call branch, executed.
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.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
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.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
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.Pq Event 89H , Umask 20H
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Qualify mispredicted indirect near calls, including
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both register and memory indirect, executed.
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.It Li BR_MISP_EXEC.NONTAKEN
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.It Li BR_MISP_EXEC.NONTAKEN
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.Pq Event 89H , Umask 40H
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Qualify mispredicted non-taken near branches
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executed,.
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.It Li BR_MISP_EXEC.TAKEN
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.It Li BR_MISP_EXEC.TAKEN
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.Pq Event 89H , Umask 80H
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Qualify mispredicted taken near branches executed.
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Must combine with 01H,02H, 04H, 08H, 10H, 20H
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.It Li BR_MISP_EXEC.ALL_BRANCHES
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.It Li BR_MISP_EXEC.ALL_BRANCHES
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.Pq Event 89H , Umask FFH
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Counts all near executed branches (not necessarily
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retired).
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.It Li IDQ_UOPS_NOT_DELIVERED.CORE
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.It Li IDQ_UOPS_NOT_DELIVERED.CORE
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.Pq Event 9CH , Umask 01H
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Count number of non-delivered uops to RAT per
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thread.
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.It Li UOPS_DISPATCHED_PORT.PORT_0
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.It Li UOPS_DISPATCHED_PORT.PORT_0
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.Pq Event A1H , Umask 01H
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Cycles which a Uop is dispatched on port 0.
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Cycles which a Uop is dispatched on port 0.
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.It Li UOPS_DISPATCHED_PORT.PORT_1
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.Pq Event A1H , Umask 02H
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Cycles which a Uop is dispatched on port 1.
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.It Li UOPS_DISPATCHED_PORT.PORT_2_LD
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Cycles which a Uop is dispatched on port 1.
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.It Li UOPS_DISPATCHED_PORT.PORT_2_LD
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.Pq Event A1H , Umask 04H
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Cycles which a load uop is dispatched on port 2.
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.It Li UOPS_DISPATCHED_PORT.PORT_2_STA
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Cycles which a load uop is dispatched on port 2.
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.It Li UOPS_DISPATCHED_PORT.PORT_2_STA
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.Pq Event A1H , Umask 08H
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Cycles which a store address uop is dispatched on
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port 2.
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.It Li UOPS_DISPATCHED_PORT.PORT_2
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.It Li UOPS_DISPATCHED_PORT.PORT_2
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.Pq Event A1H , Umask 0CH
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Cycles which a Uop is dispatched on port 2.
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.It Li UOPS_DISPATCHED_PORT.PORT_3_LD
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Cycles which a Uop is dispatched on port 2.
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.It Li UOPS_DISPATCHED_PORT.PORT_3_LD
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.Pq Event A1H , Umask 10H
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Cycles which a load uop is dispatched on port 3.
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.It Li UOPS_DISPATCHED_PORT.PORT_3_STA
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Cycles which a load uop is dispatched on port 3.
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.It Li UOPS_DISPATCHED_PORT.PORT_3_STA
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.Pq Event A1H , Umask 20H
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Cycles which a store address uop is dispatched on
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port 3.
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.It Li UOPS_DISPATCHED_PORT.PORT_3
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.It Li UOPS_DISPATCHED_PORT.PORT_3
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.Pq Event A1H , Umask 30H
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Cycles which a Uop is dispatched on port 3.
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Cycles which a Uop is dispatched on port 3.
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.It Li UOPS_DISPATCHED_PORT.PORT_4
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.Pq Event A1H , Umask 40H
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Cycles which a Uop is dispatched on port 4.
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.It Li UOPS_DISPATCHED_PORT.PORT_5
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.It Li UOPS_DISPATCHED_PORT.PORT_5
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.Pq Event A1H , Umask 80H
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Cycles which a Uop is dispatched on port 5.
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.It Li RESOURCE_STALLS.ANY
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Cycles which a Uop is dispatched on port 5.
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.It Li RESOURCE_STALLS.ANY
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.Pq Event A2H , Umask 01H
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Cycles Allocation is stalled due to Resource Related
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reason.
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.It Li RESOURCE_STALLS.LB
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.It Li RESOURCE_STALLS.LB
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.Pq Event A2H , Umask 01H
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Counts the cycles of stall due to lack of load buffers.
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.It Li RESOURCE_STALLS.RS
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Counts the cycles of stall due to lack of load buffers.
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.It Li RESOURCE_STALLS.RS
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.Pq Event A2H , Umask 04H
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Cycles stalled due to no eligible RS entry available.
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.It Li RESOURCE_STALLS.SB
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Cycles stalled due to no eligible RS entry available.
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.It Li RESOURCE_STALLS.SB
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.Pq Event A2H , Umask 08H
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Cycles stalled due to no store buffers available. (not
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including draining form sync).
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.It Li RESOURCE_STALLS.ROB
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.It Li RESOURCE_STALLS.ROB
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.Pq Event A2H , Umask 10H
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Cycles stalled due to re-order buffer full.
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.It Li RESOURCE_STALLS.FCSW
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Cycles stalled due to re-order buffer full.
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.It Li RESOURCE_STALLS.FCSW
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.Pq Event A2H , Umask 20H
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Cycles stalled due to writing the FPU control word.
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.It Li RESOURCE_STALLS.MXCSR
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Cycles stalled due to writing the FPU control word.
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.It Li RESOURCE_STALLS.MXCSR
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.Pq Event A2H , Umask 40H
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Cycles stalled due to the MXCSR register rename
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occurring to close to a previous MXCSR rename.
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.It Li RESOURCE_STALLS.OTHER
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.It Li RESOURCE_STALLS.OTHER
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.Pq Event A2H , Umask 80H
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Cycles stalled while execution was stalled due to
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other resource issues.
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.It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING
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.It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING
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.Pq Event A3H , Umask 01H
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Cycles with pending L2 miss loads. Set AnyThread
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to count per core.
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.It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING
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.It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING
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.Pq Event A3H , Umask 02H
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Cycles with pending L1 cache miss loads.Set
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AnyThread to count per core.
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.It Li CYCLE_ACTIVITY.CYCLES_NO_DISPATCH
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.It Li CYCLE_ACTIVITY.CYCLES_NO_DISPATCH
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.Pq Event A3H , Umask 04H
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Cycles of dispatch stalls. Set AnyThread to count per
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Cycles of dispatch stalls. Set AnyThread to count per
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core.
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.It Li DSB2MITE_SWITCHES.COUNT
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.It Li DSB2MITE_SWITCHES.COUNT
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.Pq Event ABH , Umask 01H
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Number of DSB to MITE switches.
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.It Li DSB2MITE_SWITCHES.PENALTY_CYCLES
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Number of DSB to MITE switches.
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.It Li DSB2MITE_SWITCHES.PENALTY_CYCLES
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.Pq Event ABH , Umask 02H
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Cycles DSB to MITE switches caused delay.
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.It Li DSB_FILL.OTHER_CANCEL
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Cycles DSB to MITE switches caused delay.
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.It Li DSB_FILL.OTHER_CANCEL
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.Pq Event ACH , Umask 02H
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Cases of cancelling valid DSB fill not because of
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exceeding way limit.
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.It Li DSB_FILL.EXCEED_DSB_LINES
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.It Li DSB_FILL.EXCEED_DSB_LINES
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.Pq Event ACH , Umask 08H
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DSB Fill encountered > 3 DSB lines.
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.It Li DSB_FILL.ALL_CANCEL
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DSB Fill encountered > 3 DSB lines.
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.It Li DSB_FILL.ALL_CANCEL
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.Pq Event ACH , Umask 0AH
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Cases of cancelling valid Decode Stream Buffer
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(DSB) fill not because of exceeding way limit.
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.It Li ITLB.ITLB_FLUSH
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.It Li ITLB.ITLB_FLUSH
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.Pq Event AEH , Umask 01H
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Counts the number of ITLB flushes, includes
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4k/2M/4M pages.
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.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD
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.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD
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.Pq Event B0H , Umask 01H
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Demand data read requests sent to uncore.
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.It Li OFFCORE_REQUESTS.DEMAND_RFO
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.It Li OFFCORE_REQUESTS.DEMAND_RFO
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.Pq Event B0H , Umask 04H
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Demand RFO read requests sent to uncore, including
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regular RFOs, locks, ItoM.
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.It Li OFFCORE_REQUESTS.ALL_DATA_RD
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.It Li OFFCORE_REQUESTS.ALL_DATA_RD
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.Pq Event B0H , Umask 08H
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Data read requests sent to uncore (demand and
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prefetch).
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.It Li UOPS_DISPATCHED.THREAD
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.It Li UOPS_DISPATCHED.THREAD
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.Pq Event B1H , Umask 01H
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Counts total number of uops to be dispatched per-
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thread each cycle. Set Cmask = 1, INV =1 to count
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stall cycles.
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.It Li UOPS_DISPATCHED.CORE
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.It Li UOPS_DISPATCHED.CORE
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.Pq Event B1H , Umask 02H
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Counts total number of uops to be dispatched per-
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core each cycle.
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.It Li OFFCORE_REQUESTS_BUFFER.SQ_FULL
|
||||
.It Li OFFCORE_REQUESTS_BUFFER.SQ_FULL
|
||||
.Pq Event B2H , Umask 01H
|
||||
Offcore requests buffer cannot take more entries
|
||||
for this thread core.
|
||||
@ -738,47 +738,47 @@ following traits: 1. addressing of the format [base +
|
||||
offset], 2. the offset is between 1 and 2047, 3. the
|
||||
address specified in the base register is in one page
|
||||
and the address [base+offset] is in another page.
|
||||
.It Li OFF_CORE_RESPONSE_0
|
||||
.It Li OFF_CORE_RESPONSE_0
|
||||
.Pq Event B7H , Umask 01H
|
||||
(Event B7H, Umask 01H) Off-core Response Performance
|
||||
Monitoring; PMC0 only. Requires programming MSR 01A6H
|
||||
.It Li OFF_CORE_RESPONSE_1
|
||||
.It Li OFF_CORE_RESPONSE_1
|
||||
.Pq Event BBH , Umask 01H
|
||||
(Event BBH, Umask 01H) Off-core Response Performance
|
||||
Monitoring; PMC3 only. Requires programming MSR 01A7H
|
||||
.It Li TLB_FLUSH.DTLB_THREAD
|
||||
.It Li TLB_FLUSH.DTLB_THREAD
|
||||
.Pq Event BDH , Umask 01H
|
||||
DTLB flush attempts of the thread-specific entries.
|
||||
.It Li TLB_FLUSH.STLB_ANY
|
||||
DTLB flush attempts of the thread-specific entries.
|
||||
.It Li TLB_FLUSH.STLB_ANY
|
||||
.Pq Event BDH , Umask 20H
|
||||
Count number of STLB flush attempts.
|
||||
.It Li L1D_BLOCKS.BANK_CONFLICT_CYCLES
|
||||
Count number of STLB flush attempts.
|
||||
.It Li L1D_BLOCKS.BANK_CONFLICT_CYCLES
|
||||
.Pq Event BFH , Umask 05H
|
||||
Cycles when dispatched loads are cancelled due to
|
||||
L1D bank conflicts with other load ports.
|
||||
.It Li INST_RETIRED.ANY_P
|
||||
.It Li INST_RETIRED.ANY_P
|
||||
.Pq Event C0H , Umask 00H
|
||||
Number of instructions at retirement.
|
||||
.It Li INST_RETIRED.ALL
|
||||
Number of instructions at retirement.
|
||||
.It Li INST_RETIRED.ALL
|
||||
.Pq Event C0H , Umask 01H
|
||||
Precise instruction retired event with HW to reduce
|
||||
effect of PEBS shadow in IP distribution.
|
||||
.It Li OTHER_ASSISTS.ITLB_MISS_RETIRED
|
||||
.Pq Event C1H , Umask 02H
|
||||
Instructions that experienced an ITLB miss.
|
||||
.It Li OTHER_ASSISTS.AVX_STORE
|
||||
Instructions that experienced an ITLB miss.
|
||||
.It Li OTHER_ASSISTS.AVX_STORE
|
||||
.Pq Event C1H , Umask 08H
|
||||
Number of assists associated with 256-bit AVX
|
||||
store operations.
|
||||
.It Li OTHER_ASSISTS.AVX_TO_SSE
|
||||
.It Li OTHER_ASSISTS.AVX_TO_SSE
|
||||
.Pq Event C1H , Umask 10H
|
||||
Number of transitions from AVX-256 to legacy SSE
|
||||
when penalty applicable.
|
||||
.It Li OTHER_ASSISTS.SSE_TO_AVX
|
||||
.It Li OTHER_ASSISTS.SSE_TO_AVX
|
||||
.Pq Event C1H , Umask 20H
|
||||
Number of transitions from SSE to AVX-256 when
|
||||
penalty applicable.
|
||||
.It Li UOPS_RETIRED.ALL
|
||||
.It Li UOPS_RETIRED.ALL
|
||||
.Pq Event C2H , Umask 01H
|
||||
Counts the number of micro-ops retired, Use
|
||||
cmask=1 and invert to count active cycles or stalled
|
||||
@ -787,7 +787,7 @@ cycles.
|
||||
.Pq Event C2H , Umask 02H
|
||||
Counts the number of retirement slots used each
|
||||
cycle.
|
||||
.It Li MACHINE_CLEARS.MEMORY_ORDERING
|
||||
.It Li MACHINE_CLEARS.MEMORY_ORDERING
|
||||
.Pq Event C3H , Umask 02H
|
||||
Counts the number of machine clears due to
|
||||
memory order conflicts.
|
||||
@ -795,25 +795,25 @@ memory order conflicts.
|
||||
.Pq Event C3H , Umask 04H
|
||||
Counts the number of times that a program writes
|
||||
to a code section.
|
||||
.It Li MACHINE_CLEARS.MASKMOV
|
||||
.It Li MACHINE_CLEARS.MASKMOV
|
||||
.Pq Event C3H , Umask 20H
|
||||
Counts the number of executed AVX masked load
|
||||
operations that refer to an illegal address range
|
||||
with the mask bits set to 0.
|
||||
.It Li BR_INST_RETIRED.ALL_BRANCH
|
||||
.It Li BR_INST_RETIRED.ALL_BRANCH
|
||||
.Pq Event C4H , Umask 00H
|
||||
Branch instructions at retirement.
|
||||
.It Li BR_INST_RETIRED.CONDITIONAL
|
||||
Branch instructions at retirement.
|
||||
.It Li BR_INST_RETIRED.CONDITIONAL
|
||||
.Pq Event C4H , Umask 01H
|
||||
Counts the number of conditional branch
|
||||
instructions retired.
|
||||
.It Li BR_INST_RETIRED.NEAR_CALL
|
||||
.It Li BR_INST_RETIRED.NEAR_CALL
|
||||
.Pq Event C4H , Umask 02H
|
||||
Direct and indirect near call instructions retired.
|
||||
.It Li BR_INST_RETIRED.ALL_BRANCHES
|
||||
Direct and indirect near call instructions retired.
|
||||
.It Li BR_INST_RETIRED.ALL_BRANCHES
|
||||
.Pq Event C4H , Umask 04H
|
||||
Counts the number of branch instructions retired.
|
||||
.It Li BR_INST_RETIRED.NEAR_RETURN
|
||||
Counts the number of branch instructions retired.
|
||||
.It Li BR_INST_RETIRED.NEAR_RETURN
|
||||
.Pq Event C4H , Umask 08H
|
||||
Counts the number of near return instructions
|
||||
retired.
|
||||
@ -823,16 +823,16 @@ Counts the number of not taken branch instructions
|
||||
retired.
|
||||
.It Li BR_INST_RETIRED.NEAR_TAKEN
|
||||
.Pq Event C4H , Umask 20H
|
||||
Number of near taken branches retired.
|
||||
Number of near taken branches retired.
|
||||
.It Li BR_INST_RETIRED.FAR_BRANCH
|
||||
.Pq Event C4H , Umask 40H
|
||||
Number of far branches retired.
|
||||
Number of far branches retired.
|
||||
.It Li BR_MISP_RETIRED.ALL_BRANCHES
|
||||
.Pq Event C5H , Umask 00H
|
||||
Mispredicted branch instructions at retirement.
|
||||
Mispredicted branch instructions at retirement.
|
||||
.It Li BR_MISP_RETIRED.CONDITIONAL
|
||||
.Pq Event C5H , Umask 01H
|
||||
Mispredicted conditional branch instructions retired.
|
||||
Mispredicted conditional branch instructions retired.
|
||||
.It Li BR_MISP_RETIRED.NEAR_CALL
|
||||
.Pq Event C5H , Umask 02H
|
||||
Direct and indirect mispredicted near call
|
||||
@ -842,25 +842,25 @@ instructions retired.
|
||||
Mispredicted macro branch instructions retired.
|
||||
.It Li BR_MISP_RETIRED.NOT_TAKEN
|
||||
.Pq Event C5H , Umask 10H
|
||||
Mispredicted not taken branch instructions retired.
|
||||
Mispredicted not taken branch instructions retired.
|
||||
.It Li BR_MISP_RETIRED.TAKEN
|
||||
.Pq Event C5H , Umask 20H
|
||||
Mispredicted taken branch instructions retired.
|
||||
Mispredicted taken branch instructions retired.
|
||||
.It Li FP_ASSIST.X87_OUTPUT
|
||||
.Pq Event CAH , Umask 02H
|
||||
Number of X87 assists due to output value.
|
||||
Number of X87 assists due to output value.
|
||||
.It Li FP_ASSIST.X87_INPUT
|
||||
.Pq Event CAH , Umask 04H
|
||||
Number of X87 assists due to input value.
|
||||
Number of X87 assists due to input value.
|
||||
.It Li FP_ASSIST.SIMD_OUTPUT
|
||||
.Pq Event CAH , Umask 08H
|
||||
Number of SIMD FP assists due to output values.
|
||||
Number of SIMD FP assists due to output values.
|
||||
.It Li FP_ASSIST.SIMD_INPUT
|
||||
.Pq Event CAH , Umask 10H
|
||||
Number of SIMD FP assists due to input values.
|
||||
Number of SIMD FP assists due to input values.
|
||||
.It Li FP_ASSIST.ANY 1EH
|
||||
.Pq Event CAH , Umask
|
||||
Cycles with any input/output SSE* or FP assists.
|
||||
Cycles with any input/output SSE* or FP assists.
|
||||
.It Li ROB_MISC_EVENTS.LBR_INSERTS
|
||||
.Pq Event CCH , Umask 20H
|
||||
Count cases of saving new LBR records by
|
||||
@ -893,27 +893,27 @@ combine with umask 01H, 02H, to produce counts.
|
||||
.Pq Event D0H , Umask
|
||||
Qualify retired memory uops with line split. Must
|
||||
combine with umask 01H, 02H, to produce counts.
|
||||
.It Li MEM_UOP_RETIRED_ALL
|
||||
.It Li MEM_UOP_RETIRED_ALL
|
||||
.Pq Event D0H , Umask
|
||||
Qualify any retired memory uops. Must combine
|
||||
with umask 01H, 02H, to produce counts.
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
|
||||
.Pq Event D1H , Umask 01H
|
||||
Retired load uops with L1 cache hits as data
|
||||
sources.
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT
|
||||
.Pq Event D1H , Umask 02H
|
||||
Retired load uops with L2 cache hits as data
|
||||
sources.
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT
|
||||
.Pq Event D1H , Umask 04H
|
||||
Retired load uops which data sources were data hits
|
||||
Retired load uops which data sources were data hits
|
||||
in LLC without snoops required.
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.LLC_MISS
|
||||
.Pq Event D1H , Umask 20H
|
||||
Retired load uops which data sources were data
|
||||
missed LLC (excluding unknown data source).
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB
|
||||
.Pq Event D1H , Umask 40H
|
||||
Retired load uops which data sources were load
|
||||
uops missed L1 but hit FB due to preceding miss to
|
||||
@ -930,58 +930,58 @@ correct prediction and this is corrected by other
|
||||
branch handling mechanisms at the front end.
|
||||
.It Li L2_TRANS.DEMAND_DATA_RD
|
||||
.Pq Event F0H , Umask 01H
|
||||
Demand Data Read requests that access L2 cache.
|
||||
Demand Data Read requests that access L2 cache.
|
||||
.It Li L2_TRANS.RFO
|
||||
.Pq Event F0H , Umask 02H
|
||||
RFO requests that access L2 cache.
|
||||
RFO requests that access L2 cache.
|
||||
.It Li L2_TRANS.CODE_RD
|
||||
.Pq Event F0H , Umask 04H
|
||||
L2 cache accesses when fetching instructions.
|
||||
L2 cache accesses when fetching instructions.
|
||||
.It Li L2_TRANS.ALL_PF
|
||||
.Pq Event F0H , Umask 08H
|
||||
L2 or LLC HW prefetches that access L2 cache.
|
||||
L2 or LLC HW prefetches that access L2 cache.
|
||||
.It Li L2_TRANS.L1D_WB
|
||||
.Pq Event F0H , Umask 10H
|
||||
L1D writebacks that access L2 cache.
|
||||
L1D writebacks that access L2 cache.
|
||||
.It Li L2_TRANS.L2_FILL
|
||||
.Pq Event F0H , Umask 20H
|
||||
L2 fill requests that access L2 cache.
|
||||
L2 fill requests that access L2 cache.
|
||||
.It Li L2_TRANS.L2_WB
|
||||
.Pq Event F0H , Umask 40H
|
||||
L2 writebacks that access L2 cache.
|
||||
L2 writebacks that access L2 cache.
|
||||
.It Li L2_TRANS.ALL_REQUESTS
|
||||
.Pq Event F0H , Umask 80H
|
||||
Transactions accessing L2 pipe.
|
||||
Transactions accessing L2 pipe.
|
||||
.It Li L2_LINES_IN.I
|
||||
.Pq Event F1H , Umask 01H
|
||||
L2 cache lines in I state filling L2.
|
||||
L2 cache lines in I state filling L2.
|
||||
.It Li L2_LINES_IN.S
|
||||
.Pq Event F1H , Umask 02H
|
||||
L2 cache lines in S state filling L2.
|
||||
.It Li L2_LINES_IN.E
|
||||
L2 cache lines in S state filling L2.
|
||||
.It Li L2_LINES_IN.E
|
||||
.Pq Event F1H , Umask 04H
|
||||
L2 cache lines in E state filling L2.
|
||||
L2 cache lines in E state filling L2.
|
||||
.It Li L2_LINES-IN.ALL
|
||||
.Pq Event F1H , Umask 07H
|
||||
L2 cache lines filling L2.
|
||||
L2 cache lines filling L2.
|
||||
.It Li L2_LINES_OUT.DEMAND_CLEAN
|
||||
.Pq Event F2H , Umask 01H
|
||||
Clean L2 cache lines evicted by demand.
|
||||
Clean L2 cache lines evicted by demand.
|
||||
.It Li L2_LINES_OUT.DEMAND_DIRTY
|
||||
.Pq Event F2H , Umask 02H
|
||||
Dirty L2 cache lines evicted by demand.
|
||||
Dirty L2 cache lines evicted by demand.
|
||||
.It Li L2_LINES_OUT.PF_CLEAN
|
||||
.Pq Event F2H , Umask 04H
|
||||
Clean L2 cache lines evicted by L2 prefetch.
|
||||
Clean L2 cache lines evicted by L2 prefetch.
|
||||
.It Li L2_LINES_OUT.PF_DIRTY
|
||||
.Pq Event F2H , Umask 08H
|
||||
Dirty L2 cache lines evicted by L2 prefetch.
|
||||
Dirty L2 cache lines evicted by L2 prefetch.
|
||||
.It Li L2_LINES_OUT.DIRTY_ALL
|
||||
.Pq Event F2H , Umask 0AH
|
||||
Dirty L2 cache lines filling the L2.
|
||||
Dirty L2 cache lines filling the L2.
|
||||
.It Li SQ_MISC.SPLIT_LOCK
|
||||
.Pq Event F4H , Umask 10H
|
||||
Split locks in SQ.
|
||||
Split locks in SQ.
|
||||
.El
|
||||
.Sh SEE ALSO
|
||||
.Xr pmc 3 ,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user