ARM: Convert spaces to tabs, fix formatting.
Not a functional change.
This commit is contained in:
Michal Meloun
parent
23c2675f0c
commit
74767d85c1
@ -98,7 +98,7 @@ __FBSDID("$FreeBSD$");
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#endif
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.Lcurpcpu:
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.word _C_LABEL(__pcpu)
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.word _C_LABEL(__pcpu)
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.Lblocked_lock:
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.word _C_LABEL(blocked_lock)
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@ -129,7 +129,7 @@ ENTRY(cpu_throw)
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#endif
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GET_PCPU(r7, r9)
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ldr r7, [r5, #(TD_PCB)] /* r7 = new thread's PCB */
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ldr r7, [r5, #(TD_PCB)] /* r7 = new thread's PCB */
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/* Switch to lwp0 context */
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@ -275,25 +275,25 @@ ENTRY(cpu_switch)
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/* rem: r2 = old PCB */
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/* rem: r9 = new PCB */
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ldr r5, [r9, #(PCB_DACR)] /* r5 = new DACR */
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ldr r5, [r9, #(PCB_DACR)] /* r5 = new DACR */
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mov r2, #DOMAIN_CLIENT
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cmp r5, r2, lsl #(PMAP_DOMAIN_KERNEL * 2) /* Sw to kernel thread? */
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beq .Lcs_context_switched /* Yup. Don't flush cache */
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mrc p15, 0, r0, c3, c0, 0 /* r0 = old DACR */
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cmp r5, r2, lsl #(PMAP_DOMAIN_KERNEL * 2) /* Sw to kernel thread? */
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beq .Lcs_context_switched /* Yup. Don't flush cache */
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mrc p15, 0, r0, c3, c0, 0 /* r0 = old DACR */
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/*
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* Get the new L1 table pointer into r11. If we're switching to
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* Get the new L1 table pointer into r11. If we're switching to
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* an LWP with the same address space as the outgoing one, we can
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* skip the cache purge and the TTB load.
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*
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* To avoid data dep stalls that would happen anyway, we try
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* and get some useful work done in the mean time.
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*/
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mrc p15, 0, r10, c2, c0, 0 /* r10 = old L1 */
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ldr r11, [r9, #(PCB_PAGEDIR)] /* r11 = new L1 */
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mrc p15, 0, r10, c2, c0, 0 /* r10 = old L1 */
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ldr r11, [r9, #(PCB_PAGEDIR)] /* r11 = new L1 */
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teq r10, r11 /* Same L1? */
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cmpeq r0, r5 /* Same DACR? */
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beq .Lcs_context_switched /* yes! */
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teq r10, r11 /* Same L1? */
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cmpeq r0, r5 /* Same DACR? */
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beq .Lcs_context_switched /* yes! */
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/*
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* Definately need to flush the cache.
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@ -375,6 +375,3 @@ ENTRY(cpu_switch)
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add r3, r9, #PCB_R4
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ldmia r3, {r4-r12, sp, pc}
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END(cpu_switch)
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@ -109,7 +109,7 @@ __FBSDID("$FreeBSD$");
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#endif
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.Lcurpcpu:
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.word _C_LABEL(__pcpu)
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.word _C_LABEL(__pcpu)
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.word PCPU_SIZE
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.Lblocked_lock:
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.word _C_LABEL(blocked_lock)
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@ -134,7 +134,7 @@ ENTRY(cpu_context_switch) /* QQQ: What about macro instead of function? */
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* it's the only place where standalone predictor flush must be
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* executed in kernel (except self modifying code case).
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*/
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mcr CP15_BPIALL /* and flush entire Branch Target Cache */
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mcr CP15_BPIALL /* flush entire Branch Target Cache */
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DSB
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mov pc, lr
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END(cpu_context_switch)
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@ -155,9 +155,9 @@ ENTRY(cpu_throw)
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bl _C_LABEL(vfp_discard) /* VFP without preserving state. */
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#endif
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GET_PCPU(r8, r9) /* r8 = current pcpu */
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ldr r4, [r8, #PC_CPUID] /* r4 = current cpu id */
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ldr r4, [r8, #PC_CPUID] /* r4 = current cpu id */
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cmp r10, #0 /* old thread? */
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cmp r10, #0 /* old thread? */
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beq 2f /* no, skip */
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/* Remove this CPU from the active list. */
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@ -206,7 +206,7 @@ ENTRY(cpu_throw)
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*/
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/* MMU switch to new thread. */
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ldr r0, [r7, #(PCB_PAGEDIR)]
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ldr r0, [r7, #(PCB_PAGEDIR)]
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#ifdef INVARIANTS
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cmp r0, #0 /* new thread? */
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beq badsw4 /* no, panic */
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@ -290,11 +290,11 @@ ENTRY(cpu_switch)
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* it is time to restore them for the new thread. However,
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* some registers are not safe over function call.
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*/
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mov r9, r2 /* r9 = lock */
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mov r9, r2 /* r9 = lock */
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mov r10, r0 /* r10 = oldtd */
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mov r11, r1 /* r11 = newtd */
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GET_PCPU(r8, r3) /* r8 = current PCPU */
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GET_PCPU(r8, r3) /* r8 = current PCPU */
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ldr r7, [r11, #(TD_PCB)] /* r7 = newtd->td_pcb */
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@ -341,8 +341,8 @@ ENTRY(cpu_switch)
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ldr r6, [r6, #P_VMSPACE] /* newtd->proc->vmspace */
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add r6, #VM_PMAP /* newtd->proc->vmspace->pmap */
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ldr r5, [r8, #PC_CURPMAP] /* get old curpmap */
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str r6, [r8, #PC_CURPMAP] /* and save new one */
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ldr r5, [r8, #PC_CURPMAP] /* get old curpmap */
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str r6, [r8, #PC_CURPMAP] /* and save new one */
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mov r0, #PM_ACTIVE
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add r5, r0 /* r5 = old pm_active */
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@ -376,7 +376,7 @@ ENTRY(cpu_switch)
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#endif
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/* Set cpu to new active list. */
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#ifdef SMP
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1: ldrex r0, [r6]
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1: ldrex r0, [r6]
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orr r0, r2
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strex r1, r0, [r6]
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teq r1, #0
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@ -427,7 +427,7 @@ sw1:
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beq 1b
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#endif
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/* Set the new tls */
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ldr r0, [r11, #(TD_MD + MD_TP)]
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ldr r0, [r11, #(TD_MD + MD_TP)]
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mcr CP15_TPIDRURO(r0) /* write tls thread reg 2 */
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/* We have a new curthread now so make a note it */
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@ -450,7 +450,7 @@ badsw1:
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ldr r0, =sw1_panic_str
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bl _C_LABEL(panic)
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1: nop
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b 1b
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b 1b
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badsw2:
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ldr r0, =sw2_panic_str
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