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Add an option CPU_ATHLON_SSE_HACK which attempts to enable the SSE

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feature bit on newer Athlon CPUs if the BIOS has forgotten to enable
it.

This patch was constructed using some info made available by John
Clemens at http://www.deater.net/john/PavilionN5430.html

Reviewed by:	-audit
MFC after:	3 weeks
This commit is contained in:
dwmalone 2002-02-12 21:13:02 +00:00
parent d48667d57b
commit 74fa509202
6 changed files with 46 additions and 0 deletions
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18
sys/amd64/amd64/initcpu.c
View File

@ -575,6 +575,24 @@ initializecpu(void)
init_mendocino();
break;
}
} else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
#if defined(I686_CPU) && defined(CPU_ATHLON_SSE_HACK)
/*
* Sometimes the BIOS doesn't enable SSE instructions.
* According to AMD document 20734, the mobile
* Duron, the (mobile) Athlon 4 and the Athlon MP
* support SSE. These correspond to cpu_id 0x66X
* or 0x67X.
*/
if ((cpu_feature & CPUID_XMM) == 0 &&
((cpu_id & ~0xf) == 0x660 ||
(cpu_id & ~0xf) == 0x670)) {
u_int regs[4];
wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000);
do_cpuid(1, regs);
cpu_feature = regs[3];
}
#endif
}
break;
#endif

4
sys/conf/NOTES
View File

@ -175,6 +175,9 @@ cpu I686_CPU # aka Pentium Pro(tm)
#
# Options for CPU features.
#
# CPU_ATHLON_SSE_HACK tries to enable SSE instructions when the BIOS has
# forgotten to enable them.
#
# CPU_BLUELIGHTNING_FPU_OP_CACHE enables FPU operand cache on IBM
# BlueLightning CPU. It works only with Cyrix FPU, and this option
# should not be used with Intel FPU.
@ -256,6 +259,7 @@ cpu I686_CPU # aka Pentium Pro(tm)
# NOTE 3: This option may cause failures for software that requires
# locked cycles in order to operate correctly.
#
options CPU_ATHLON_SSE_HACK
options CPU_BLUELIGHTNING_FPU_OP_CACHE
options CPU_BLUELIGHTNING_3X
options CPU_BTB_EN

1
sys/conf/options.i386
View File

@ -64,6 +64,7 @@ CYRIX_CACHE_WORKS opt_cpu.h
CYRIX_CACHE_REALLY_WORKS opt_cpu.h
NO_MEMORY_HOLE opt_cpu.h
CPU_ENABLE_SSE opt_cpu.h
CPU_ATHLON_SSE_HACK opt_cpu.h
# The CPU type affects the endian conversion functions all over the kernel.
I386_CPU opt_global.h

1
sys/conf/options.pc98
View File

@ -64,6 +64,7 @@ CYRIX_CACHE_WORKS opt_cpu.h
CYRIX_CACHE_REALLY_WORKS opt_cpu.h
NO_MEMORY_HOLE opt_cpu.h
CPU_ENABLE_SSE opt_cpu.h
CPU_ATHLON_SSE_HACK opt_cpu.h
# The CPU type affects the endian conversion functions all over the kernel.
I386_CPU opt_global.h

4
sys/i386/conf/NOTES
View File

@ -175,6 +175,9 @@ cpu I686_CPU # aka Pentium Pro(tm)
#
# Options for CPU features.
#
# CPU_ATHLON_SSE_HACK tries to enable SSE instructions when the BIOS has
# forgotten to enable them.
#
# CPU_BLUELIGHTNING_FPU_OP_CACHE enables FPU operand cache on IBM
# BlueLightning CPU. It works only with Cyrix FPU, and this option
# should not be used with Intel FPU.
@ -256,6 +259,7 @@ cpu I686_CPU # aka Pentium Pro(tm)
# NOTE 3: This option may cause failures for software that requires
# locked cycles in order to operate correctly.
#
options CPU_ATHLON_SSE_HACK
options CPU_BLUELIGHTNING_FPU_OP_CACHE
options CPU_BLUELIGHTNING_3X
options CPU_BTB_EN

18
sys/i386/i386/initcpu.c
View File

@ -575,6 +575,24 @@ initializecpu(void)
init_mendocino();
break;
}
} else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
#if defined(I686_CPU) && defined(CPU_ATHLON_SSE_HACK)
/*
* Sometimes the BIOS doesn't enable SSE instructions.
* According to AMD document 20734, the mobile
* Duron, the (mobile) Athlon 4 and the Athlon MP
* support SSE. These correspond to cpu_id 0x66X
* or 0x67X.
*/
if ((cpu_feature & CPUID_XMM) == 0 &&
((cpu_id & ~0xf) == 0x660 ||
(cpu_id & ~0xf) == 0x670)) {
u_int regs[4];
wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000);
do_cpuid(1, regs);
cpu_feature = regs[3];
}
#endif
}
break;
#endif