A couple of months' worth of back-burner hacking: restructure to better
handle the minor (but significant) differences between the various Vortex chips; add (incomplete) support for playback.
This commit is contained in:
des
parent
efae2cbb66
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7526d14d48
@ -37,6 +37,103 @@
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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/***************************************************************************\
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* *
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* SUPPORTED CHIPSETS *
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* *
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\***************************************************************************/
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static struct au88x0_chipset au88x0_chipsets[] = {
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{
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.auc_name = "Aureal Vortex (8820)",
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.auc_pci_id = 0x000112eb,
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.auc_control = 0x1280c,
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.auc_irq_source = 0x12800,
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.auc_irq_mask = 0x12804,
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.auc_irq_control = 0x12808,
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.auc_irq_status = 0x1199c,
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.auc_dma_control = 0x1060c,
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.auc_fifo_size = 0x20,
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.auc_wt_fifos = 32,
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.auc_wt_fifo_base = 0x0e800,
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.auc_wt_fifo_ctl = 0x0f800,
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.auc_wt_dma_ctl = 0x10500,
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.auc_adb_fifos = 16,
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.auc_adb_fifo_base = 0x0e000,
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.auc_adb_fifo_ctl = 0x0f840,
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.auc_adb_dma_ctl = 0x10580,
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.auc_adb_route_base = 0x10800,
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.auc_adb_route_bits = 7,
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.auc_adb_codec_in = 0x48,
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.auc_adb_codec_out = 0x58,
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},
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{
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.auc_name = "Aureal Vortex 2 (8830)",
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.auc_pci_id = 0x000212eb,
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.auc_control = 0x2a00c,
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.auc_irq_source = 0x2a000,
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.auc_irq_mask = 0x2a004,
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.auc_irq_control = 0x2a008,
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.auc_irq_status = 0x2919c,
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.auc_dma_control = 0x27ae8,
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.auc_fifo_size = 0x40,
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.auc_wt_fifos = 64,
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.auc_wt_fifo_base = 0x10000,
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.auc_wt_fifo_ctl = 0x16000,
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.auc_wt_dma_ctl = 0x27900,
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.auc_adb_fifos = 32,
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.auc_adb_fifo_base = 0x14000,
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.auc_adb_fifo_ctl = 0x16100,
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.auc_adb_dma_ctl = 0x27a00,
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.auc_adb_route_base = 0x28000,
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.auc_adb_route_bits = 8,
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.auc_adb_codec_in = 0x70,
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.auc_adb_codec_out = 0x88,
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},
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{
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.auc_name = "Aureal Vortex Advantage (8810)",
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.auc_pci_id = 0x000312eb,
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.auc_control = 0x2a00c,
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.auc_irq_source = 0x2a000,
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.auc_irq_mask = 0x2a004,
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.auc_irq_control = 0x2a008,
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.auc_irq_status = 0x2919c,
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.auc_dma_control = 0x27ae8,
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.auc_fifo_size = 0x20,
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.auc_wt_fifos = 32,
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.auc_wt_fifo_base = 0x10000,
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.auc_wt_fifo_ctl = 0x16000,
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.auc_wt_dma_ctl = 0x27fd8,
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.auc_adb_fifos = 16,
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.auc_adb_fifo_base = 0x14000,
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.auc_adb_fifo_ctl = 0x16100,
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.auc_adb_dma_ctl = 0x27180,
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.auc_adb_route_base = 0x28000,
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.auc_adb_route_bits = 8,
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.auc_adb_codec_in = 0x70,
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.auc_adb_codec_out = 0x88,
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},
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{
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.auc_pci_id = 0,
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}
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};
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/***************************************************************************\
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* *
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@ -343,12 +440,13 @@ static void
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au88x0_intr(void *arg)
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{
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struct au88x0_info *aui = arg;
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struct au88x0_chipset *auc = aui->aui_chipset;
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int pending, source;
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pending = au88x0_read(aui, AU88X0_IRQ_PENDING, 4);
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pending = au88x0_read(aui, auc->auc_irq_control, 4);
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if ((pending & AU88X0_IRQ_PENDING_BIT) == 0)
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return;
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source = au88x0_read(aui, AU88X0_IRQ_SOURCE, 4);
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source = au88x0_read(aui, auc->auc_irq_source, 4);
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if (source & AU88X0_IRQ_FATAL_ERR)
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device_printf(aui->aui_dev,
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"fatal error interrupt received\n");
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@ -358,8 +456,8 @@ au88x0_intr(void *arg)
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/* XXX handle the others... */
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/* acknowledge the interrupts we just handled */
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au88x0_write(aui, AU88X0_IRQ_SOURCE, source, 4);
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au88x0_read(aui, AU88X0_IRQ_SOURCE, 4);
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au88x0_write(aui, auc->auc_irq_source, source, 4);
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au88x0_read(aui, auc->auc_irq_source, 4);
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}
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@ -377,19 +475,20 @@ au88x0_intr(void *arg)
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static void
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au88x0_fifo_init(struct au88x0_info *aui)
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{
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struct au88x0_chipset *auc = aui->aui_chipset;
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int i;
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/* reset, then clear the ADB FIFOs */
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for (i = 0; i < AU88X0_ADB_FIFOS; ++i)
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au88x0_write(aui, AU88X0_ADB_FIFO_CTL + i * 4, 0x42000, 4);
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for (i = 0; i < AU88X0_ADB_FIFOS * AU88X0_ADB_FIFO_SIZE; ++i)
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au88x0_write(aui, AU88X0_ADB_FIFO_BASE + i * 4, 0, 4);
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for (i = 0; i < auc->auc_adb_fifos; ++i)
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au88x0_write(aui, auc->auc_adb_fifo_ctl + i * 4, 0x42000, 4);
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for (i = 0; i < auc->auc_adb_fifos * auc->auc_fifo_size; ++i)
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au88x0_write(aui, auc->auc_adb_fifo_base + i * 4, 0, 4);
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/* reset, then clear the WT FIFOs */
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for (i = 0; i < AU88X0_WT_FIFOS; ++i)
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au88x0_write(aui, AU88X0_WT_FIFO_CTL + i * 4, 0x42000, 4);
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for (i = 0; i < AU88X0_WT_FIFOS * AU88X0_WT_FIFO_SIZE; ++i)
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au88x0_write(aui, AU88X0_WT_FIFO_BASE + i * 4, 0, 4);
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for (i = 0; i < auc->auc_wt_fifos; ++i)
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au88x0_write(aui, auc->auc_wt_fifo_ctl + i * 4, 0x42000, 4);
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for (i = 0; i < auc->auc_wt_fifos * auc->auc_fifo_size; ++i)
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au88x0_write(aui, auc->auc_wt_fifo_base + i * 4, 0, 4);
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}
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/*
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@ -398,15 +497,16 @@ au88x0_fifo_init(struct au88x0_info *aui)
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static void
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au88x0_init(struct au88x0_info *aui)
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{
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struct au88x0_chipset *auc = aui->aui_chipset;
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/* reset the chip */
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au88x0_write(aui, AU88X0_CONTROL, 0xffffffff, 4);
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au88x0_write(aui, auc->auc_control, 0xffffffff, 4);
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DELAY(10000);
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/* clear all interrupts */
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au88x0_write(aui, AU88X0_IRQ_SOURCE, 0xffffffff, 4);
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au88x0_read(aui, AU88X0_IRQ_SOURCE, 4);
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au88x0_read(aui, AU88X0_IRQ_STATUS, 4);
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au88x0_write(aui, auc->auc_irq_source, 0xffffffff, 4);
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au88x0_read(aui, auc->auc_irq_source, 4);
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au88x0_read(aui, auc->auc_irq_status, 4);
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/* initialize the codec */
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au88x0_codec_init(aui);
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@ -416,7 +516,7 @@ au88x0_init(struct au88x0_info *aui)
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/* initialize the DMA engine */
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/* XXX chicken-waving! */
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au88x0_write(aui, AU88X0_DMA_CONTROL, 0x1380000, 4);
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au88x0_write(aui, auc->auc_dma_control, 0x1380000, 4);
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}
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/*
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@ -448,18 +548,17 @@ au88x0_set_status(device_t dev)
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static int
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au88x0_pci_probe(device_t dev)
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{
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struct au88x0_chipset *auc;
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uint32_t pci_id;
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switch (pci_get_devid(dev)) {
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case AUREAL_VORTEX_2:
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device_set_desc(dev, "Aureal Vortex 2");
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return (0);
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case AUREAL_VORTEX_ADVANTAGE:
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device_set_desc(dev, "Aureal Vortex Advantage");
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return (0);
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default:
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return (ENXIO);
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pci_id = pci_get_devid(dev);
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for (auc = au88x0_chipsets; auc->auc_pci_id; ++auc) {
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if (auc->auc_pci_id == pci_id) {
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device_set_desc(dev, auc->auc_name);
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return (0);
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}
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}
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return (0);
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return (ENXIO);
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}
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/*
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@ -468,6 +567,7 @@ au88x0_pci_probe(device_t dev)
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static int
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au88x0_pci_attach(device_t dev)
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{
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struct au88x0_chipset *auc;
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struct au88x0_info *aui = NULL;
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uint32_t config;
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int error;
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@ -480,15 +580,11 @@ au88x0_pci_attach(device_t dev)
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/* Model-specific parameters */
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aui->aui_model = pci_get_devid(dev);
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switch (aui->aui_model) {
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case AUREAL_VORTEX_1:
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break;
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case AUREAL_VORTEX_2:
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case AUREAL_VORTEX_ADVANTAGE:
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break;
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default:
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for (auc = au88x0_chipsets; auc->auc_pci_id; ++auc)
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if (auc->auc_pci_id == aui->aui_model)
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aui->aui_chipset = auc;
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if (aui->aui_chipset == NULL)
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panic("%s() called for non-au88x0 device", __func__);
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}
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/* enable pio, mmio, bus-mastering dma */
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config = pci_read_config(dev, PCIR_COMMAND, 2);
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@ -567,8 +663,8 @@ au88x0_pci_attach(device_t dev)
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/* register with the pcm driver */
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if (pcm_register(dev, aui, 0, 0))
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goto failed;
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#if 0
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pcm_addchan(dev, PCMDIR_PLAY, &au88x0_chan_class, aui);
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#if 0
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pcm_addchan(dev, PCMDIR_REC, &au88x0_chan_class, aui);
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#endif
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au88x0_set_status(dev);
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@ -31,6 +31,56 @@
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#ifndef _AU88X0_H_INCLUDED
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#define _AU88X0_H_INCLUDED
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/*
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* Chipset parameters
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*/
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struct au88x0_chipset {
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const char *auc_name;
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uint32_t auc_pci_id;
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/* General control register */
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uint32_t auc_control;
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#define AU88X0_CTL_MIDI_ENABLE 0x0001
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#define AU88X0_CTL_GAME_ENABLE 0x0008
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#define AU88X0_CTL_IRQ_ENABLE 0x4000
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/* IRQ control register */
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uint32_t auc_irq_source;
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#define AU88X0_IRQ_FATAL_ERR 0x0001
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#define AU88X0_IRQ_PARITY_ERR 0x0002
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#define AU88X0_IRQ_REG_ERR 0x0004
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#define AU88X0_IRQ_FIFO_ERR 0x0008
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#define AU88X0_IRQ_DMA_ERR 0x0010
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#define AU88X0_IRQ_PCMOUT 0x0020
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#define AU88X0_IRQ_TIMER 0x1000
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#define AU88X0_IRQ_MIDI 0x2000
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#define AU88X0_IRQ_MODEM 0x4000
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uint32_t auc_irq_mask;
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uint32_t auc_irq_control;
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#define AU88X0_IRQ_PENDING_BIT 0x0001
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uint32_t auc_irq_status;
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/* DMA control registers */
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uint32_t auc_dma_control;
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/* FIFOs */
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int auc_fifo_size;
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int auc_wt_fifos;
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uint32_t auc_wt_fifo_base;
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uint32_t auc_wt_fifo_ctl;
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uint32_t auc_wt_dma_ctl;
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int auc_adb_fifos;
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uint32_t auc_adb_fifo_base;
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uint32_t auc_adb_fifo_ctl;
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uint32_t auc_adb_dma_ctl;
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/* Routing */
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uint32_t auc_adb_route_base;
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int auc_adb_route_bits;
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int auc_adb_codec_in;
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int auc_adb_codec_out;
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};
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/*
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* Channel information
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*/
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@ -48,9 +98,16 @@ struct au88x0_info {
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/* the device we're associated with */
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device_t aui_dev;
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uint32_t aui_model;
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struct au88x0_chipset *aui_chipset;
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/* parameters */
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bus_size_t aui_bufsize;
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int aui_wt_fifos;
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int aui_wt_fifo_ctl;
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int aui_adb_fifos;
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int aui_adb_fifo_ctl;
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int aui_fifo_size;
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uint32_t aui_chanbase;
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/* bus_space tag and handle */
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bus_space_tag_t aui_spct;
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@ -77,13 +134,6 @@ struct au88x0_info {
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struct au88x0_chan_info aui_chan[2];
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};
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/*
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* PCI IDs of supported cards
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*/
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#define AUREAL_VORTEX_1 0x000112eb /* 8820 (not supported) */
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#define AUREAL_VORTEX_2 0x000212eb /* 8830 */
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#define AUREAL_VORTEX_ADVANTAGE 0x000312eb /* 8810 */
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/*
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* Common parameters
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*/
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@ -93,30 +143,6 @@ struct au88x0_info {
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#define AU88X0_BUFSIZE_DFLT 0x4000
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#define AU88X0_BUFSIZE_MAX 0x4000
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/*
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* General control registers
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*/
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#define AU88X0_CONTROL 0x2a00c
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#define AU88X0_CTL_MIDI_ENABLE 0x0001
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#define AU88X0_CTL_GAME_ENABLE 0x0008
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#define AU88X0_CTL_IRQ_ENABLE 0x4000
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#define AU88X0_IRQ_SOURCE 0x2a000
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#define AU88X0_IRQ_MASK 0x2a004
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#define AU88X0_IRQ_FATAL_ERR 0x0001
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#define AU88X0_IRQ_PARITY_ERR 0x0002
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#define AU88X0_IRQ_REG_ERR 0x0004
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#define AU88X0_IRQ_FIFO_ERR 0x0008
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#define AU88X0_IRQ_DMA_ERR 0x0010
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#define AU88X0_IRQ_PCMOUT 0x0020
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#define AU88X0_IRQ_TIMER 0x1000
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#define AU88X0_IRQ_MIDI 0x2000
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#define AU88X0_IRQ_MODEM 0x4000
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#define AU88X0_IRQ_PENDING 0x2a008
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#define AU88X0_IRQ_PENDING_BIT 0x0001
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#define AU88X0_IRQ_STATUS 0x2919c
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#define AU88X0_DMA_CONTROL 0x27ae8
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/*
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* Codec control registers
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*
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@ -149,26 +175,4 @@ struct au88x0_info {
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(((d) << AU88X0_CDIO_DATA_SHIFT) & AU88X0_CDIO_DATA_MASK))
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#define AU88X0_CODEC_ENABLE 0x29190
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/*
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* FIFO and DMA contorl registers
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*
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* There are two sets of these, one for PCM audio (ADB) and one for
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* wavetables (WT).
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*/
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#define AU88X0_ADB_FIFOS 32
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#define AU88X0_ADB_FIFO_CTL 0x16100
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#define AU88X0_ADB_FIFO_BASE 0x14000
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#define AU88X0_ADB_FIFO_SIZE 0x40
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#define AU8810_ADB_DMA_CTL 0x27180
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#define AU8820_ADB_DMA_CTL 0x10580
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#define AU8830_ADB_DMA_CTL 0x27a00
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#define AU88X0_WT_FIFOS 32
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#define AU88X0_WT_FIFO_CTL 0x16000
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#define AU88X0_WT_FIFO_BASE 0x10000
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#define AU88X0_WT_FIFO_SIZE 0x40
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#define AU8810_WT_DMA_CTL 0x27fd8
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#define AU8820_WT_DMA_CTL 0x10500
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#define AU8830_WT_DMA_CTL 0x27900
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#endif
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