Add the PG_NX support for i386/PAE.
Reviewed by: alc
This commit is contained in:
ru
parent
d4909d3f26
commit
754d500925
@ -188,20 +188,6 @@ printcpuinfo(void)
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}
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}
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/* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
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if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
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strcmp(cpu_vendor, "AuthenticAMD") == 0) {
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if (cpu_exthigh >= 0x80000001) {
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do_cpuid(0x80000001, regs);
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amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
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amd_feature2 = regs[2];
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}
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if (cpu_exthigh >= 0x80000008) {
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do_cpuid(0x80000008, regs);
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cpu_procinfo2 = regs[2];
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}
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}
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if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
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if ((cpu_id & 0xf00) > 0x300) {
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u_int brand_index;
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@ -1104,7 +1090,20 @@ finishidentcpu(void)
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u_char ccr3;
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u_int regs[4];
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if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
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/* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
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if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
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strcmp(cpu_vendor, "AuthenticAMD") == 0) {
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init_exthigh();
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if (cpu_exthigh >= 0x80000001) {
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do_cpuid(0x80000001, regs);
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amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
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amd_feature2 = regs[2];
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}
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if (cpu_exthigh >= 0x80000008) {
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do_cpuid(0x80000008, regs);
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cpu_procinfo2 = regs[2];
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}
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} else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
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if (cpu == CPU_486) {
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/*
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* These conditions are equivalent to:
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@ -41,6 +41,9 @@ __FBSDID("$FreeBSD$");
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#include <machine/md_var.h>
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#include <machine/specialreg.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
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#define CPU_ENABLE_SSE
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#endif
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@ -686,6 +689,15 @@ initializecpu(void)
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break;
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}
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}
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#ifdef PAE
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if ((amd_feature & AMDID_NX) != 0) {
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uint64_t msr;
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msr = rdmsr(MSR_EFER) | EFER_NXE;
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wrmsr(MSR_EFER, msr);
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pg_nx = PG_NX;
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}
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#endif
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break;
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#endif
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default:
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@ -211,7 +211,7 @@ minidumpsys(struct dumperinfo *di)
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j = va >> PDRSHIFT;
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if ((pd[j] & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
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/* This is an entire 2M page. */
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pa = pd[j] & PG_FRAME & ~PDRMASK;
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pa = pd[j] & PG_PS_FRAME;
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for (k = 0; k < NPTEPG; k++) {
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if (is_dumpable(pa))
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dump_add_page(pa);
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@ -310,7 +310,7 @@ minidumpsys(struct dumperinfo *di)
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j = va >> PDRSHIFT;
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if ((pd[j] & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
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/* This is a single 2M block. Generate a fake PTP */
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pa = pd[j] & PG_FRAME & ~PDRMASK;
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pa = pd[j] & PG_PS_FRAME;
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for (k = 0; k < NPTEPG; k++) {
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fakept[k] = (pa + (k * PAGE_SIZE)) | PG_V | PG_RW | PG_A | PG_M;
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}
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@ -206,6 +206,7 @@ vm_offset_t kernel_vm_end;
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extern u_int32_t KERNend;
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#ifdef PAE
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pt_entry_t pg_nx;
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static uma_zone_t pdptzone;
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#endif
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@ -958,7 +959,7 @@ pmap_extract(pmap_t pmap, vm_offset_t va)
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pde = pmap->pm_pdir[va >> PDRSHIFT];
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if (pde != 0) {
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if ((pde & PG_PS) != 0) {
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rtval = (pde & ~PDRMASK) | (va & PDRMASK);
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rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
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PMAP_UNLOCK(pmap);
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return rtval;
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}
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@ -991,7 +992,7 @@ pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
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if (pde != 0) {
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if (pde & PG_PS) {
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if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
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m = PHYS_TO_VM_PAGE((pde & ~PDRMASK) |
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m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
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(va & PDRMASK));
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vm_page_hold(m);
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}
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@ -1365,7 +1366,7 @@ pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags)
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* hold count, and activate it.
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*/
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if (ptepa) {
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m = PHYS_TO_VM_PAGE(ptepa);
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m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
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m->wire_count++;
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} else {
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/*
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@ -1498,7 +1499,8 @@ pmap_release(pmap_t pmap)
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mtx_unlock_spin(&allpmaps_lock);
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for (i = 0; i < NPGPTD; i++)
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ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i]);
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ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
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PG_FRAME);
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bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
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sizeof(*pmap->pm_pdir));
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@ -1946,7 +1948,7 @@ pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va)
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pmap_invalidate_page(kernel_pmap, va);
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pmap->pm_stats.resident_count -= 1;
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if (oldpte & PG_MANAGED) {
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m = PHYS_TO_VM_PAGE(oldpte);
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m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
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if (oldpte & PG_M) {
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KASSERT((oldpte & PG_RW),
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("pmap_remove_pte: modified page not writable: va: %#x, pte: %#jx",
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@ -2154,8 +2156,14 @@ pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
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return;
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}
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#ifdef PAE
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if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
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(VM_PROT_WRITE|VM_PROT_EXECUTE))
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return;
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#else
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if (prot & VM_PROT_WRITE)
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return;
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#endif
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anychanged = 0;
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@ -2163,7 +2171,8 @@ pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
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sched_pin();
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PMAP_LOCK(pmap);
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for (; sva < eva; sva = pdnxt) {
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unsigned obits, pbits, pdirindex;
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pt_entry_t obits, pbits;
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unsigned pdirindex;
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pdnxt = (sva + NBPDR) & ~PDRMASK;
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@ -2181,7 +2190,12 @@ pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
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* Check for large page.
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*/
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if ((ptpaddr & PG_PS) != 0) {
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pmap->pm_pdir[pdirindex] &= ~(PG_M|PG_RW);
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if ((prot & VM_PROT_WRITE) == 0)
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pmap->pm_pdir[pdirindex] &= ~(PG_M|PG_RW);
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#ifdef PAE
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if ((prot & VM_PROT_EXECUTE) == 0)
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pmap->pm_pdir[pdirindex] |= pg_nx;
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#endif
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anychanged = 1;
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continue;
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}
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@ -2199,27 +2213,39 @@ pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
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* size, PG_RW, PG_A, and PG_M are among the least
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* significant 32 bits.
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*/
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obits = pbits = *(u_int *)pte;
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obits = pbits = *pte;
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if ((pbits & PG_V) == 0)
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continue;
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if (pbits & PG_MANAGED) {
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m = NULL;
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if (pbits & PG_A) {
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m = PHYS_TO_VM_PAGE(*pte);
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m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
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vm_page_flag_set(m, PG_REFERENCED);
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pbits &= ~PG_A;
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}
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if ((pbits & PG_M) != 0) {
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if (m == NULL)
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m = PHYS_TO_VM_PAGE(*pte);
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m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
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vm_page_dirty(m);
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}
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}
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pbits &= ~(PG_RW | PG_M);
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if ((prot & VM_PROT_WRITE) == 0)
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pbits &= ~(PG_RW | PG_M);
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#ifdef PAE
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if ((prot & VM_PROT_EXECUTE) == 0)
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pbits |= pg_nx;
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#endif
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if (pbits != obits) {
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#ifdef PAE
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if (!atomic_cmpset_64(pte, obits, pbits))
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goto retry;
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#else
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if (!atomic_cmpset_int((u_int *)pte, obits,
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pbits))
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goto retry;
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#endif
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if (obits & PG_G)
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pmap_invalidate_page(pmap, sva);
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else
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@ -2384,6 +2410,10 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
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newpte |= PG_RW;
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vm_page_flag_set(m, PG_WRITEABLE);
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}
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#ifdef PAE
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if ((prot & VM_PROT_EXECUTE) == 0)
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newpte |= pg_nx;
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#endif
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if (wired)
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newpte |= PG_W;
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if (va < VM_MAXUSER_ADDRESS)
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@ -2404,6 +2434,11 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
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vm_page_flag_set(om, PG_REFERENCED);
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if (opa != VM_PAGE_TO_PHYS(m))
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invlva = TRUE;
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#ifdef PAE
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if ((origpte & PG_NX) == 0 &&
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(newpte & PG_NX) != 0)
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invlva = TRUE;
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#endif
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}
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if (origpte & PG_M) {
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KASSERT((origpte & PG_RW),
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@ -2514,7 +2549,7 @@ pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
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if (ptepa) {
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if (ptepa & PG_PS)
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panic("pmap_enter_quick: unexpected mapping into 4MB page");
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mpte = PHYS_TO_VM_PAGE(ptepa);
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mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
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mpte->wire_count++;
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} else {
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mpte = _pmap_allocpte(pmap, ptepindex,
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@ -2560,6 +2595,10 @@ pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
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pmap->pm_stats.resident_count++;
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pa = VM_PAGE_TO_PHYS(m);
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#ifdef PAE
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if ((prot & VM_PROT_EXECUTE) == 0)
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pa |= pg_nx;
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#endif
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/*
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* Now validate mapping with RO protection
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@ -2746,7 +2785,7 @@ pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
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continue;
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}
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srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
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srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
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if (srcmpte->wire_count == 0)
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panic("pmap_copy: source page table page is unused");
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@ -2990,7 +3029,7 @@ pmap_remove_pages(pmap_t pmap)
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continue;
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}
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m = PHYS_TO_VM_PAGE(tpte);
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m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
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KASSERT(m->phys_addr == (tpte & PG_FRAME),
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("vm_page_t %p phys_addr mismatch %016jx %016jx",
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m, (uintmax_t)m->phys_addr,
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@ -3521,7 +3560,7 @@ pmap_pid_dump(int pid)
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pt_entry_t pa;
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vm_page_t m;
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pa = *pte;
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m = PHYS_TO_VM_PAGE(pa);
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m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
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printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
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va, pa, m->hold_count, m->wire_count, m->flags);
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npte++;
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@ -736,8 +736,16 @@ trap_pfault(frame, usermode, eva)
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map = &vm->vm_map;
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}
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/*
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* PGEX_I is defined only if the execute disable bit capability is
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* supported and enabled.
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*/
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if (frame->tf_err & PGEX_W)
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ftype = VM_PROT_WRITE;
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#ifdef PAE
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else if ((frame->tf_err & PGEX_I) && pg_nx != 0)
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ftype = VM_PROT_EXECUTE;
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#endif
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else
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ftype = VM_PROT_READ;
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@ -63,12 +63,21 @@
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#define PG_AVAIL2 0x400 /* < programmers use */
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#define PG_AVAIL3 0x800 /* \ */
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#define PG_PDE_PAT 0x1000 /* PAT PAT index */
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#ifdef PAE
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#define PG_NX (1ull<<63) /* No-execute */
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#endif
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/* Our various interpretations of the above */
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#define PG_W PG_AVAIL1 /* "Wired" pseudoflag */
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#define PG_MANAGED PG_AVAIL2
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#define PG_FRAME (~((vm_paddr_t)PAGE_MASK))
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#ifdef PAE
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#define PG_FRAME (0x000ffffffffff000ull)
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#define PG_PS_FRAME (0x000fffffffe00000ull)
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#else
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#define PG_FRAME (~PAGE_MASK)
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#define PG_PS_FRAME (0xffc00000)
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#endif
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#define PG_PROT (PG_RW|PG_U) /* all protection bits . */
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#define PG_N (PG_NC_PWT|PG_NC_PCD) /* Non-cacheable */
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@ -79,6 +88,7 @@
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#define PGEX_P 0x01 /* Protection violation vs. not present */
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#define PGEX_W 0x02 /* during a Write cycle */
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#define PGEX_U 0x04 /* access from User mode (UPL) */
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#define PGEX_I 0x10 /* during an instruction fetch */
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/*
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* Size of Kernel address space. This is the number of page table pages
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@ -201,7 +211,7 @@ pmap_kextract(vm_offset_t va)
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vm_paddr_t pa;
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if ((pa = PTD[va >> PDRSHIFT]) & PG_PS) {
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pa = (pa & ~(NBPDR - 1)) | (va & (NBPDR - 1));
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pa = (pa & PG_PS_FRAME) | (va & PDRMASK);
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} else {
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pa = *vtopte(va);
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pa = (pa & PG_FRAME) | (va & PAGE_MASK);
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@ -238,10 +248,33 @@ pte_load_store(pt_entry_t *ptep, pt_entry_t v)
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return (r);
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}
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/* XXXRU move to atomic.h? */
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static __inline int
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atomic_cmpset_64(volatile uint64_t *dst, uint64_t exp, uint64_t src)
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{
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int64_t res = exp;
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__asm __volatile (
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" lock ; "
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" cmpxchg8b %2 ; "
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" setz %%al ; "
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" movzbl %%al,%0 ; "
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"# atomic_cmpset_64"
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: "+A" (res), /* 0 (result) */
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"=m" (*dst) /* 1 */
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: "m" (*dst), /* 2 */
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"b" ((uint32_t)src),
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"c" ((uint32_t)(src >> 32)));
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return (res);
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}
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#define pte_load_clear(ptep) pte_load_store((ptep), (pt_entry_t)0ULL)
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#define pte_store(ptep, pte) pte_load_store((ptep), (pt_entry_t)pte)
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extern pt_entry_t pg_nx;
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#else /* PAE */
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static __inline pt_entry_t
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@ -67,6 +67,11 @@
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#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
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#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
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/*
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* Bits in AMD64 special registers. EFER is 64 bits wide.
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*/
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#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
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/*
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* CPUID instruction features register
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*/
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@ -420,6 +425,9 @@
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#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
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#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
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/* AMD64 MSR's */
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#define MSR_EFER 0xc0000080 /* extended features */
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/* VIA ACE crypto featureset: for via_feature_rng */
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#define VIA_HAS_RNG 1 /* cpu has RNG */
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@ -43,7 +43,9 @@
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* Machine dependent constants for 386.
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*/
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#ifndef PAE
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#define VM_PROT_READ_IS_EXEC /* if you can read -- then you can exec */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Virtual memory related constants, all in bytes
|
||||
|
||||
Loading…
Reference in New Issue
Block a user