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MFC r272730,273018:

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Add support for QAC AR816x/AR817x Gigabit/Fast Ethernet controllers.
  These controllers seem to have the same feature of AR813x/AR815x and
  improved RSS support(4 TX queues and 8 RX queues).  alc(4) supports
  all hardware features except RSS.  I didn't implement RX checksum
  offloading for AR816x/AR817x just because I couldn't get
  confirmation from the Vendor whether AR816x/AR817x corrected its
  predecessor's RX checksum offloading bug on fragmented packets.
  This change adds supports for the following controllers.
   o AR8161 PCIe Gigabit Ethernet controller
   o AR8162 PCIe Fast Ethernet controller
   o AR8171 PCIe Gigabit Ethernet controller
   o AR8172 PCIe Fast Ethernet controller
   o Killer E2200 Gigabit Ethernet controller

  Relnotes:	yes
This commit is contained in:
yongari 2014-10-21 04:48:49 +00:00
parent b882f9e15f
commit 7595869074
3 changed files with 1386 additions and 222 deletions
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1291
sys/dev/alc/if_alc.c
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File diff suppressed because it is too large Load Diff

310
sys/dev/alc/if_alcreg.h
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@ -44,10 +44,26 @@
#define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */
#define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */
#define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */
#define DEVICEID_ATHEROS_AR8161 0x1091
#define DEVICEID_ATHEROS_E2200 0xE091
#define DEVICEID_ATHEROS_AR8162 0x1090
#define DEVICEID_ATHEROS_AR8171 0x10A1
#define DEVICEID_ATHEROS_AR8172 0x10A0
#define ATHEROS_AR8152_B_V10 0xC0
#define ATHEROS_AR8152_B_V11 0xC1
/*
* Atheros AR816x/AR817x revisions
*/
#define AR816X_REV_A0 0
#define AR816X_REV_A1 1
#define AR816X_REV_B0 2
#define AR816X_REV_C0 3
#define AR816X_REV_SHIFT 3
#define AR816X_REV(x) ((x) >> AR816X_REV_SHIFT)
/* 0x0000 - 0x02FF : PCIe configuration space */
#define ALC_PEX_UNC_ERR_SEV 0x10C
@ -63,11 +79,34 @@
#define PEX_UNC_ERR_SEV_ECRC 0x00080000
#define PEX_UNC_ERR_SEV_UR 0x00100000
#define ALC_EEPROM_LD 0x204 /* AR816x */
#define EEPROM_LD_START 0x00000001
#define EEPROM_LD_IDLE 0x00000010
#define EEPROM_LD_DONE 0x00000000
#define EEPROM_LD_PROGRESS 0x00000020
#define EEPROM_LD_EXIST 0x00000100
#define EEPROM_LD_EEPROM_EXIST 0x00000200
#define EEPROM_LD_FLASH_EXIST 0x00000400
#define EEPROM_LD_FLASH_END_ADDR_MASK 0x03FF0000
#define EEPROM_LD_FLASH_END_ADDR_SHIFT 16
#define ALC_TWSI_CFG 0x218
#define TWSI_CFG_SW_LD_START 0x00000800
#define TWSI_CFG_HW_LD_START 0x00001000
#define TWSI_CFG_LD_EXIST 0x00400000
#define ALC_SLD 0x218 /* AR816x */
#define SLD_START 0x00000800
#define SLD_PROGRESS 0x00001000
#define SLD_IDLE 0x00002000
#define SLD_SLVADDR_MASK 0x007F0000
#define SLD_EXIST 0x00800000
#define SLD_FREQ_MASK 0x03000000
#define SLD_FREQ_100K 0x00000000
#define SLD_FREQ_200K 0x01000000
#define SLD_FREQ_300K 0x02000000
#define SLD_FREQ_400K 0x03000000
#define ALC_PCIE_PHYMISC 0x1000
#define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004
@ -77,6 +116,9 @@
#define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16
#define PCIE_PHYMISC2_SERDES_TH_SHIFT 18
#define ALC_PDLL_TRNS1 0x1104
#define PDLL_TRNS1_D3PLLOFF_ENB 0x00000800
#define ALC_TWSI_DEBUG 0x1108
#define TWSI_DEBUG_DEV_EXIST 0x20000000
@ -103,11 +145,14 @@
#define PM_CFG_SERDES_PD_EX_L1 0x00000040
#define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080
#define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00
#define PM_CFG_RX_L1_AFTER_L0S 0x00000800
#define PM_CFG_ASPM_L0S_ENB 0x00001000
#define PM_CFG_CLK_SWH_L1 0x00002000
#define PM_CFG_CLK_PWM_VER1_1 0x00004000
#define PM_CFG_PCIE_RECV 0x00008000
#define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000
#define PM_CFG_L1_ENTRY_TIMER_816X_MASK 0x00070000
#define PM_CFG_TX_L1_AFTER_L0S 0x00080000
#define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000
#define PM_CFG_LCKDET_TIMER_MASK 0x0F000000
#define PM_CFG_EN_BUFS_RX_L0S 0x10000000
@ -121,8 +166,10 @@
#define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6
#define PM_CFG_L1_ENTRY_TIMER_DEFAULT 1
#define PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT 4
#define PM_CFG_LCKDET_TIMER_DEFAULT 12
#define PM_CFG_PM_REQ_TIMER_DEFAULT 12
#define PM_CFG_PM_REQ_TIMER_816X_DEFAULT 15
#define ALC_LTSSM_ID_CFG 0x12FC
#define LTSSM_ID_WRO_ENB 0x00001000
@ -131,6 +178,7 @@
#define MASTER_RESET 0x00000001
#define MASTER_TEST_MODE_MASK 0x0000000C
#define MASTER_BERT_START 0x00000010
#define MASTER_WAKEN_25M 0x00000020
#define MASTER_OOB_DIS_OFF 0x00000040
#define MASTER_SA_TIMER_ENB 0x00000080
#define MASTER_MTIMER_ENB 0x00000100
@ -171,7 +219,7 @@
*/
#define ALC_IM_TX_TIMER_DEFAULT 1000 /* 1ms */
#define ALC_GPHY_CFG 0x140C /* 16bits */
#define ALC_GPHY_CFG 0x140C /* 16 bits, 32 bits on AR816x */
#define GPHY_CFG_EXT_RESET 0x0001
#define GPHY_CFG_RTL_MODE 0x0002
#define GPHY_CFG_LED_MODE 0x0004
@ -188,6 +236,7 @@
#define GPHY_CFG_PHY_PLL_ON 0x2000
#define GPHY_CFG_PWDOWN_HW 0x4000
#define GPHY_CFG_PHY_PLL_BYPASS 0x8000
#define GPHY_CFG_100AB_ENB 0x00020000
#define ALC_IDLE_STATUS 0x1410
#define IDLE_STATUS_RXMAC 0x00000001
@ -212,9 +261,10 @@
#define MDIO_CLK_25_10 0x04000000
#define MDIO_CLK_25_14 0x05000000
#define MDIO_CLK_25_20 0x06000000
#define MDIO_CLK_25_28 0x07000000
#define MDIO_CLK_25_128 0x07000000
#define MDIO_OP_BUSY 0x08000000
#define MDIO_AP_ENB 0x10000000
#define MDIO_MODE_EXT 0x40000000
#define MDIO_DATA_SHIFT 0
#define MDIO_REG_ADDR_SHIFT 16
@ -248,6 +298,23 @@
#define SERDES_MAC_CLK_SLOWDOWN 0x00020000
#define SERDES_PHY_CLK_SLOWDOWN 0x00040000
#define ALC_LPI_CTL 0x1440
#define LPI_CTL_ENB 0x00000001
#define ALC_EXT_MDIO 0x1448
#define EXT_MDIO_REG_MASK 0x0000FFFF
#define EXT_MDIO_DEVADDR_MASK 0x001F0000
#define EXT_MDIO_REG_SHIFT 0
#define EXT_MDIO_DEVADDR_SHIFT 16
#define EXT_MDIO_REG(x) \
(((x) << EXT_MDIO_REG_SHIFT) & EXT_MDIO_REG_MASK)
#define EXT_MDIO_DEVADDR(x) \
(((x) << EXT_MDIO_DEVADDR_SHIFT) & EXT_MDIO_DEVADDR_MASK)
#define ALC_IDLE_DECISN_TIMER 0x1474
#define IDLE_DECISN_TIMER_DEFAULT_1MS 0x400
#define ALC_MAC_CFG 0x1480
#define MAC_CFG_TX_ENB 0x00000001
#define MAC_CFG_RX_ENB 0x00000002
@ -278,6 +345,7 @@
#define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000
#define MAC_CFG_HASH_ALG_CRC32 0x20000000
#define MAC_CFG_SPEED_MODE_SW 0x40000000
#define MAC_CFG_FAST_PAUSE 0x80000000
#define MAC_CFG_PREAMBLE_SHIFT 10
#define MAC_CFG_PREAMBLE_DEFAULT 7
@ -378,8 +446,12 @@
#define ALC_RSS_IDT_TABLE0 0x14E0
#define ALC_TD_PRI2_HEAD_ADDR_LO 0x14E0 /* AR816x */
#define ALC_RSS_IDT_TABLE1 0x14E4
#define ALC_TD_PRI3_HEAD_ADDR_LO 0x14E4 /* AR816x */
#define ALC_RSS_IDT_TABLE2 0x14E8
#define ALC_RSS_IDT_TABLE3 0x14EC
@ -422,6 +494,8 @@
#define ALC_SRAM_RX_FIFO_ADDR 0x1520
#define ALC_SRAM_RX_FIFO_LEN 0x1524
#define SRAM_RX_FIFO_LEN_MASK 0x00000FFF
#define SRAM_RX_FIFO_LEN_SHIFT 0
#define ALC_SRAM_TX_FIFO_ADDR 0x1528
@ -478,8 +552,12 @@
#define ALC_TDH_HEAD_ADDR_LO 0x157C
#define ALC_TD_PRI1_HEAD_ADDR_LO 0x157C /* AR816x */
#define ALC_TDL_HEAD_ADDR_LO 0x1580
#define ALC_TD_PRI0_HEAD_ADDR_LO 0x1580 /* AR816x */
#define ALC_TD_RING_CNT 0x1584
#define TD_RING_CNT_MASK 0x0000FFFF
#define TD_RING_CNT_SHIFT 0
@ -499,6 +577,7 @@
#define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */
#define TSO_OFFLOAD_THRESH_MASK 0x000007FF
#define TSO_OFFLOAD_ERRLGPKT_DROP_ENB 0x00000800
#define TSO_OFFLOAD_THRESH_SHIFT 0
#define TSO_OFFLOAD_THRESH_UNIT 8
#define TSO_OFFLOAD_THRESH_UNIT_SHIFT 3
@ -546,6 +625,17 @@
(RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | \
RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB)
/* AR816x specific bits */
#define RXQ_CFG_816X_RSS_HASH_IPV4 0x00000004
#define RXQ_CFG_816X_RSS_HASH_IPV4_TCP 0x00000008
#define RXQ_CFG_816X_RSS_HASH_IPV6 0x00000010
#define RXQ_CFG_816X_RSS_HASH_IPV6_TCP 0x00000020
#define RXQ_CFG_816X_RSS_HASH_MASK 0x0000003C
#define RXQ_CFG_816X_IPV6_PARSE_ENB 0x00000080
#define RXQ_CFG_816X_IDT_TBL_SIZE_MASK 0x0001FF00
#define RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT 8
#define RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT 0x100
#define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */
#define RX_RD_FREE_THRESH_HI_MASK 0x0000003F
#define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0
@ -559,6 +649,12 @@
#define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000
#define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0
#define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16
/*
* Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) +
* rx-packet(1522) + delay-of-link(64)
* = 3212.
*/
#define RX_FIFO_PAUSE_816X_RSVD 3212
#define ALC_RD_DMA_CFG 0x15AC
#define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */
@ -582,6 +678,7 @@
#define DMA_CFG_OUT_ORDER 0x00000004
#define DMA_CFG_RCB_64 0x00000000
#define DMA_CFG_RCB_128 0x00000008
#define DMA_CFG_PEND_AUTO_RST 0x00000008
#define DMA_CFG_RD_BURST_128 0x00000000
#define DMA_CFG_RD_BURST_256 0x00000010
#define DMA_CFG_RD_BURST_512 0x00000020
@ -601,6 +698,14 @@
#define DMA_CFG_SMB_ENB 0x00200000
#define DMA_CFG_CMB_NOW 0x00400000
#define DMA_CFG_SMB_DIS 0x01000000
#define DMA_CFG_RD_CHNL_SEL_MASK 0x0C000000
#define DMA_CFG_RD_CHNL_SEL_1 0x00000000
#define DMA_CFG_RD_CHNL_SEL_2 0x04000000
#define DMA_CFG_RD_CHNL_SEL_3 0x08000000
#define DMA_CFG_RD_CHNL_SEL_4 0x0C000000
#define DMA_CFG_WSRAM_RDCTL 0x10000000
#define DMA_CFG_RD_PEND_CLR 0x20000000
#define DMA_CFG_WR_PEND_CLR 0x40000000
#define DMA_CFG_SMB_NOW 0x80000000
#define DMA_CFG_RD_BURST_MASK 0x07
#define DMA_CFG_RD_BURST_SHIFT 4
@ -623,6 +728,12 @@
#define CMB_TX_TIMER_MASK 0x0000FFFF
#define CMB_TX_TIMER_SHIFT 0
#define ALC_MSI_MAP_TBL1 0x15D0
#define ALC_MSI_ID_MAP 0x15D4
#define ALC_MSI_MAP_TBL2 0x15D8
#define ALC_MBOX_RD0_PROD_IDX 0x15E0
#define ALC_MBOX_RD1_PROD_IDX 0x15E4
@ -640,12 +751,20 @@
#define MBOX_TD_PROD_HI_IDX_SHIFT 0
#define MBOX_TD_PROD_LO_IDX_SHIFT 16
#define ALC_MBOX_TD_PRI1_PROD_IDX 0x15F0 /* 16 bits AR816x */
#define ALC_MBOX_TD_PRI0_PROD_IDX 0x15F2 /* 16 bits AR816x */
#define ALC_MBOX_TD_CONS_IDX 0x15F4
#define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF
#define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000
#define MBOX_TD_CONS_HI_IDX_SHIFT 0
#define MBOX_TD_CONS_LO_IDX_SHIFT 16
#define ALC_MBOX_TD_PRI1_CONS_IDX 0x15F4 /* 16 bits AR816x */
#define ALC_MBOX_TD_PRI0_CONS_IDX 0x15F6 /* 16 bits AR816x */
#define ALC_MBOX_RD01_CONS_IDX 0x15F8
#define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF
#define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000
@ -674,7 +793,7 @@
#define INTR_GPHY 0x00001000
#define INTR_GPHY_LOW_PW 0x00002000
#define INTR_TXQ_TO_RST 0x00004000
#define INTR_TX_PKT 0x00008000
#define INTR_TX_PKT0 0x00008000
#define INTR_RX_PKT0 0x00010000
#define INTR_RX_PKT1 0x00020000
#define INTR_RX_PKT2 0x00040000
@ -688,6 +807,15 @@
#define INTR_PHY_LINK_DOWN 0x04000000
#define INTR_DIS_INT 0x80000000
/* INTR status for AR816x/AR817x 4 TX queues, 8 RX queues */
#define INTR_TX_PKT1 0x00000020
#define INTR_TX_PKT2 0x00000040
#define INTR_TX_PKT3 0x00000080
#define INTR_RX_PKT4 0x08000000
#define INTR_RX_PKT5 0x10000000
#define INTR_RX_PKT6 0x20000000
#define INTR_RX_PKT7 0x40000000
/* Interrupt Mask Register */
#define ALC_INTR_MASK 0x1604
@ -699,6 +827,7 @@
(INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN | \
INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN)
#else
#define INTR_TX_PKT INTR_TX_PKT0
#define INTR_RX_PKT INTR_RX_PKT0
#define INTR_RD_UNDERRUN INTR_RD0_UNDERRUN
#endif
@ -720,11 +849,54 @@
#define HDS_CFG_BACKFILLSIZE_SHIFT 8
#define HDS_CFG_MAX_HDRSIZE_SHIFT 20
#define ALC_MBOX_TD_PRI3_PROD_IDX 0x1618 /* 16 bits AR816x */
#define ALC_MBOX_TD_PRI2_PROD_IDX 0x161A /* 16 bits AR816x */
#define ALC_MBOX_TD_PRI3_CONS_IDX 0x161C /* 16 bits AR816x */
#define ALC_MBOX_TD_PRI2_CONS_IDX 0x161E /* 16 bits AR816x */
/* AR813x/AR815x registers for MAC statistics */
#define ALC_RX_MIB_BASE 0x1700
#define ALC_TX_MIB_BASE 0x1760
#define ALC_DRV 0x1804 /* AR816x */
#define DRV_ASPM_SPD10LMT_1M 0x00000000
#define DRV_ASPM_SPD10LMT_10M 0x00000001
#define DRV_ASPM_SPD10LMT_100M 0x00000002
#define DRV_ASPM_SPD10LMT_NO 0x00000003
#define DRV_ASPM_SPD10LMT_MASK 0x00000003
#define DRV_ASPM_SPD100LMT_1M 0x00000000
#define DRV_ASPM_SPD100LMT_10M 0x00000004
#define DRV_ASPM_SPD100LMT_100M 0x00000008
#define DRV_ASPM_SPD100LMT_NO 0x0000000C
#define DRV_ASPM_SPD100LMT_MASK 0x0000000C
#define DRV_ASPM_SPD1000LMT_100M 0x00000000
#define DRV_ASPM_SPD1000LMT_NO 0x00000010
#define DRV_ASPM_SPD1000LMT_1M 0x00000020
#define DRV_ASPM_SPD1000LMT_10M 0x00000030
#define DRV_ASPM_SPD1000LMT_MASK 0x00000000
#define DRV_WOLCAP_BIOS_EN 0x00000100
#define DRV_WOLMAGIC_EN 0x00000200
#define DRV_WOLLINKUP_EN 0x00000400
#define DRV_WOLPATTERN_EN 0x00000800
#define DRV_AZ_EN 0x00001000
#define DRV_WOLS5_BIOS_EN 0x00010000
#define DRV_WOLS5_EN 0x00020000
#define DRV_DISABLE 0x00040000
#define DRV_PHY_MASK 0x1FE00000
#define DRV_PHY_EEE 0x00200000
#define DRV_PHY_APAUSE 0x00400000
#define DRV_PHY_PAUSE 0x00800000
#define DRV_PHY_DUPLEX 0x01000000
#define DRV_PHY_10 0x02000000
#define DRV_PHY_100 0x04000000
#define DRV_PHY_1000 0x08000000
#define DRV_PHY_AUTO 0x10000000
#define DRV_PHY_SHIFT 21
#define ALC_CLK_GATING_CFG 0x1814
#define CLK_GATING_DMAW_ENB 0x0001
#define CLK_GATING_DMAR_ENB 0x0002
@ -737,6 +909,52 @@
#define ALC_DEBUG_DATA1 0x1904
#define ALC_MSI_RETRANS_TIMER 0x1920
#define MSI_RETRANS_TIMER_MASK 0x0000FFFF
#define MSI_RETRANS_MASK_SEL_STD 0x00000000
#define MSI_RETRANS_MASK_SEL_LINE 0x00010000
#define MSI_RETRANS_TIMER_SHIFT 0
#define ALC_WRR 0x1938
#define WRR_PRI0_MASK 0x0000001F
#define WRR_PRI1_MASK 0x00001F00
#define WRR_PRI2_MASK 0x001F0000
#define WRR_PRI3_MASK 0x1F000000
#define WRR_PRI_RESTRICT_MASK 0x60000000
#define WRR_PRI_RESTRICT_ALL 0x00000000
#define WRR_PRI_RESTRICT_HI 0x20000000
#define WRR_PRI_RESTRICT_HI2 0x40000000
#define WRR_PRI_RESTRICT_NONE 0x60000000
#define WRR_PRI0_SHIFT 0
#define WRR_PRI1_SHIFT 8
#define WRR_PRI2_SHIFT 16
#define WRR_PRI3_SHIFT 24
#define WRR_PRI_DEFAULT 4
#define WRR_PRI_RESTRICT_SHIFT 29
#define ALC_HQTD_CFG 0x193C
#define HQTD_CFG_Q1_BURST_MASK 0x0000000F
#define HQTD_CFG_Q2_BURST_MASK 0x000000F0
#define HQTD_CFG_Q3_BURST_MASK 0x00000F00
#define HQTD_CFG_BURST_ENB 0x80000000
#define HQTD_CFG_Q1_BURST_SHIFT 0
#define HQTD_CFG_Q2_BURST_SHIFT 4
#define HQTD_CFG_Q3_BURST_SHIFT 8
#define ALC_MISC 0x19C0
#define MISC_INTNLOSC_OPEN 0x00000008
#define MISC_ISO_ENB 0x00001000
#define MISC_PSW_OCP_MASK 0x00E00000
#define MISC_PSW_OCP_SHIFT 21
#define MISC_PSW_OCP_DEFAULT 7
#define ALC_MISC2 0x19C8
#define MISC2_CALB_START 0x00000001
#define ALC_MISC3 0x19CC
#define MISC3_25M_NOTO_INTNL 0x00000001
#define MISC3_25M_BY_SW 0x00000002
#define ALC_MII_DBG_ADDR 0x1D
#define ALC_MII_DBG_DATA 0x1E
@ -756,6 +974,9 @@
#define ANA_SEL_CLK125M_DSP 0x8000
#define ANA_MANUL_SWICH_ON_SHIFT 1
#define MII_DBG_ANACTL 0x00
#define DBG_ANACTL_DEFAULT 0x02EF
#define MII_ANA_CFG4 0x04
#define ANA_IECHO_ADJ_MASK 0x0F
#define ANA_IECHO_ADJ_3_MASK 0x000F
@ -767,6 +988,9 @@
#define ANA_IECHO_ADJ_1_SHIFT 8
#define ANA_IECHO_ADJ_0_SHIFT 12
#define MII_DBG_SYSMODCTL 0x04
#define DBG_SYSMODCTL_DEFAULT 0xBB8B
#define MII_ANA_CFG5 0x05
#define ANA_SERDES_CDR_BW_MASK 0x0003
#define ANA_MS_PAD_DBG 0x0004
@ -783,9 +1007,17 @@
#define ANA_SERDES_CDR_BW_SHIFT 0
#define ANA_SERDES_TH_LOS_SHIFT 4
#define MII_DBG_SRDSYSMOD 0x05
#define DBG_SRDSYSMOD_DEFAULT 0x2C46
#define MII_ANA_CFG11 0x0B
#define ANA_PS_HIB_EN 0x8000
#define MII_DBG_HIBNEG 0x0B
#define DBG_HIBNEG_HIB_PULSE 0x1000
#define DBG_HIBNEG_PSHIB_EN 0x8000
#define DBG_HIBNEG_DEFAULT 0xBC40
#define MII_ANA_CFG18 0x12
#define ANA_TEST_MODE_10BT_01MASK 0x0003
#define ANA_LOOP_SEL_10BT 0x0004
@ -800,9 +1032,36 @@
#define ANA_TRIGGER_SEL_TIMER_SHIFT 12
#define ANA_INTERVAL_SEL_TIMER_SHIFT 14
#define MII_DBG_TST10BTCFG 0x12
#define DBG_TST10BTCFG_DEFAULT 0x4C04
#define MII_DBG_AZ_ANADECT 0x15
#define DBG_AZ_ANADECT_DEFAULT 0x3220
#define DBG_AZ_ANADECT_LONG 0x3210
#define MII_DBG_MSE16DB 0x18
#define DBG_MSE16DB_UP 0x05EA
#define DBG_MSE16DB_DOWN 0x02EA
#define MII_DBG_MSE20DB 0x1C
#define DBG_MSE20DB_TH_MASK 0x01FC
#define DBG_MSE20DB_TH_DEFAULT 0x2E
#define DBG_MSE20DB_TH_HI 0x54
#define DBG_MSE20DB_TH_SHIFT 2
#define MII_DBG_AGC 0x23
#define DBG_AGC_2_VGA_MASK 0x3F00
#define DBG_AGC_2_VGA_SHIFT 8
#define DBG_AGC_LONG1G_LIMT 40
#define DBG_AGC_LONG100M_LIMT 44
#define MII_ANA_CFG41 0x29
#define ANA_TOP_PS_EN 0x8000
#define MII_DBG_LEGCYPS 0x29
#define DBG_LEGCYPS_ENB 0x8000
#define DBG_LEGCYPS_DEFAULT 0x129D
#define MII_ANA_CFG54 0x36
#define ANA_LONG_CABLE_TH_100_MASK 0x003F
#define ANA_DESERVED 0x0040
@ -813,6 +1072,51 @@
#define ANA_LONG_CABLE_TH_100_SHIFT 0
#define ANA_SHORT_CABLE_TH_100_SHIFT 8
#define MII_DBG_TST100BTCFG 0x36
#define DBG_TST100BTCFG_DEFAULT 0xE12C
#define MII_DBG_GREENCFG 0x3B
#define DBG_GREENCFG_DEFAULT 0x7078
#define MII_DBG_GREENCFG2 0x3D
#define DBG_GREENCFG2_GATE_DFSE_EN 0x0080
#define DBG_GREENCFG2_BP_GREEN 0x8000
/* Device addr 3 */
#define MII_EXT_PCS 3
#define MII_EXT_CLDCTL3 0x8003
#define EXT_CLDCTL3_BP_CABLE1TH_DET_GT 0x8000
#define MII_EXT_CLDCTL5 0x8005
#define EXT_CLDCTL5_BP_VD_HLFBIAS 0x4000
#define MII_EXT_CLDCTL6 0x8006
#define EXT_CLDCTL6_CAB_LEN_MASK 0x00FF
#define EXT_CLDCTL6_CAB_LEN_SHIFT 0
#define EXT_CLDCTL6_CAB_LEN_SHORT1G 116
#define EXT_CLDCTL6_CAB_LEN_SHORT100M 152
#define MII_EXT_VDRVBIAS 0x8062
#define EXT_VDRVBIAS_DEFAULT 3
/* Device addr 7 */
#define MII_EXT_ANEG 7
#define MII_EXT_ANEG_LOCAL_EEEADV 0x3C
#define ANEG_LOCA_EEEADV_100BT 0x0002
#define ANEG_LOCA_EEEADV_1000BT 0x0004
#define MII_EXT_ANEG_AFE 0x801A
#define ANEG_AFEE_10BT_100M_TH 0x0040
#define MII_EXT_ANEG_S3DIG10 0x8023
#define ANEG_S3DIG10_SL 0x0001
#define ANEG_S3DIG10_DEFAULT 0
#define MII_EXT_ANEG_NLP78 0x8027
#define ANEG_NLP78_120M_DEFAULT 0x8A05
/* Statistics counters collected by the MAC. */
struct smb {
/* Rx stats. */

7
sys/dev/alc/if_alcvar.h
View File

@ -52,6 +52,10 @@
/* Water mark to kick reclaiming Tx buffers. */
#define ALC_TX_DESC_HIWAT ((ALC_TX_RING_CNT * 6) / 10)
/*
* AR816x controllers support up to 16 messages but this driver
* uses single message.
*/
#define ALC_MSI_MESSAGES 1
#define ALC_MSIX_MESSAGES 1
@ -224,12 +228,13 @@ struct alc_softc {
#define ALC_FLAG_PM 0x0010
#define ALC_FLAG_FASTETHER 0x0020
#define ALC_FLAG_JUMBO 0x0040
#define ALC_FLAG_ASPM_MON 0x0080
#define ALC_FLAG_CMB_BUG 0x0100
#define ALC_FLAG_SMB_BUG 0x0200
#define ALC_FLAG_L0S 0x0400
#define ALC_FLAG_L1S 0x0800
#define ALC_FLAG_APS 0x1000
#define ALC_FLAG_AR816X_FAMILY 0x2000
#define ALC_FLAG_LINK_WAR 0x4000
#define ALC_FLAG_LINK 0x8000
struct callout alc_tick_ch;