MFC: Change the PCI-X register constants to be relative to the PCI-X PCI
capability and expand the constants some. Update ahc(4) to track the changes.
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jhb
parent
4c38c81a18
commit
773c3e841b
@ -1244,6 +1244,9 @@ struct ahd_softc {
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/* PCI cacheline size. */
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u_int pci_cachesize;
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/* PCI-X capability offset. */
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int pcix_ptr;
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/* IO Cell Parameters */
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uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS];
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@ -342,7 +342,12 @@ ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry)
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error = entry->setup(ahd);
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if (error != 0)
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return (error);
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/*
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* Find the PCI-X cap pointer. If we don't find it,
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* pcix_ptr will be 0.
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*/
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pci_find_extcap(ahd->dev_softc, PCIY_PCIX, &ahd->pcix_ptr);
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devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
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if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
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ahd->chip |= AHD_PCI;
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@ -350,6 +355,8 @@ ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry)
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ahd->bugs &= ~AHD_PCIX_BUG_MASK;
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} else {
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ahd->chip |= AHD_PCIX;
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if (ahd->pcix_ptr == 0)
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return (ENXIO);
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}
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ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
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@ -867,16 +874,16 @@ ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
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uint8_t sg_split_status1[2];
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ahd_mode_state saved_modes;
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u_int i;
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uint16_t pcix_status;
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uint32_t pcix_status;
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/*
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* Check for splits in all modes. Modes 0 and 1
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* additionally have SG engine splits to look at.
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*/
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pcix_status = aic_pci_read_config(ahd->dev_softc, PCIXR_STATUS,
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/*bytes*/2);
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pcix_status = aic_pci_read_config(ahd->dev_softc,
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ahd->pcix_ptr + PCIXR_STATUS, /*bytes*/ 4);
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printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
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ahd_name(ahd), pcix_status);
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ahd_name(ahd), pcix_status >> 16);
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saved_modes = ahd_save_modes(ahd);
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for (i = 0; i < 4; i++) {
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ahd_set_modes(ahd, i, i);
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@ -922,8 +929,8 @@ ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
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/*
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* Clear PCI-X status bits.
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*/
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aic_pci_write_config(ahd->dev_softc, PCIXR_STATUS,
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pcix_status, /*bytes*/2);
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aic_pci_write_config(ahd->dev_softc, ahd->pcix_ptr + PCIXR_STATUS,
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pcix_status, /*bytes*/4);
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ahd_outb(ahd, CLRINT, CLRSPLTINT);
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ahd_restore_modes(ahd, saved_modes);
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}
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@ -413,21 +413,77 @@
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#define PCIR_MSI_PENDING 0x14
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/* PCI-X definitions */
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#define PCIXR_COMMAND 0x96
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#define PCIXR_DEVADDR 0x98
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#define PCIXM_DEVADDR_FNUM 0x0003 /* Function Number */
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#define PCIXM_DEVADDR_DNUM 0x00F8 /* Device Number */
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#define PCIXM_DEVADDR_BNUM 0xFF00 /* Bus Number */
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#define PCIXR_STATUS 0x9A
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#define PCIXM_STATUS_64BIT 0x0001 /* Active 64bit connection to device. */
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#define PCIXM_STATUS_133CAP 0x0002 /* Device is 133MHz capable */
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#define PCIXM_STATUS_SCDISC 0x0004 /* Split Completion Discarded */
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#define PCIXM_STATUS_UNEXPSC 0x0008 /* Unexpected Split Completion */
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#define PCIXM_STATUS_CMPLEXDEV 0x0010 /* Device Complexity (set == bridge) */
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#define PCIXM_STATUS_MAXMRDBC 0x0060 /* Maximum Burst Read Count */
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#define PCIXM_STATUS_MAXSPLITS 0x0380 /* Maximum Split Transactions */
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#define PCIXM_STATUS_MAXCRDS 0x1C00 /* Maximum Cumulative Read Size */
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#define PCIXM_STATUS_RCVDSCEM 0x2000 /* Received a Split Comp w/Error msg */
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/* For header type 0 devices */
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#define PCIXR_COMMAND 0x2
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#define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */
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#define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */
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#define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */
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#define PCIXM_COMMAND_MAX_READ_512 0x0000
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#define PCIXM_COMMAND_MAX_READ_1024 0x0004
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#define PCIXM_COMMAND_MAX_READ_2048 0x0008
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#define PCIXM_COMMAND_MAX_READ_4096 0x000c
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#define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */
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#define PCIXM_COMMAND_MAX_SPLITS_1 0x0000
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#define PCIXM_COMMAND_MAX_SPLITS_2 0x0010
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#define PCIXM_COMMAND_MAX_SPLITS_3 0x0020
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#define PCIXM_COMMAND_MAX_SPLITS_4 0x0030
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#define PCIXM_COMMAND_MAX_SPLITS_8 0x0040
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#define PCIXM_COMMAND_MAX_SPLITS_12 0x0050
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#define PCIXM_COMMAND_MAX_SPLITS_16 0x0060
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#define PCIXM_COMMAND_MAX_SPLITS_32 0x0070
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#define PCIXM_COMMAND_VERSION 0x3000
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#define PCIXR_STATUS 0x4
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#define PCIXM_STATUS_DEVFN 0x000000FF
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#define PCIXM_STATUS_BUS 0x0000FF00
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#define PCIXM_STATUS_64BIT 0x00010000
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#define PCIXM_STATUS_133CAP 0x00020000
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#define PCIXM_STATUS_SC_DISCARDED 0x00040000
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#define PCIXM_STATUS_UNEXP_SC 0x00080000
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#define PCIXM_STATUS_COMPLEX_DEV 0x00100000
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#define PCIXM_STATUS_MAX_READ 0x00600000
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#define PCIXM_STATUS_MAX_READ_512 0x00000000
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#define PCIXM_STATUS_MAX_READ_1024 0x00200000
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#define PCIXM_STATUS_MAX_READ_2048 0x00400000
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#define PCIXM_STATUS_MAX_READ_4096 0x00600000
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#define PCIXM_STATUS_MAX_SPLITS 0x03800000
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#define PCIXM_STATUS_MAX_SPLITS_1 0x00000000
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#define PCIXM_STATUS_MAX_SPLITS_2 0x00800000
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#define PCIXM_STATUS_MAX_SPLITS_3 0x01000000
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#define PCIXM_STATUS_MAX_SPLITS_4 0x01800000
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#define PCIXM_STATUS_MAX_SPLITS_8 0x02000000
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#define PCIXM_STATUS_MAX_SPLITS_12 0x02800000
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#define PCIXM_STATUS_MAX_SPLITS_16 0x03000000
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#define PCIXM_STATUS_MAX_SPLITS_32 0x03800000
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#define PCIXM_STATUS_MAX_CUM_READ 0x1C000000
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#define PCIXM_STATUS_RCVD_SC_ERR 0x20000000
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#define PCIXM_STATUS_266CAP 0x40000000
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#define PCIXM_STATUS_533CAP 0x80000000
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/* For header type 1 devices (PCI-X bridges) */
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#define PCIXR_SEC_STATUS 0x2
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#define PCIXM_SEC_STATUS_64BIT 0x0001
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#define PCIXM_SEC_STATUS_133CAP 0x0002
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#define PCIXM_SEC_STATUS_SC_DISC 0x0004
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#define PCIXM_SEC_STATUS_UNEXP_SC 0x0008
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#define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010
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#define PCIXM_SEC_STATUS_SR_DELAYED 0x0020
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#define PCIXM_SEC_STATUS_BUS_MODE 0x03c0
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#define PCIXM_SEC_STATUS_VERSION 0x3000
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#define PCIXM_SEC_STATUS_266CAP 0x4000
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#define PCIXM_SEC_STATUS_533CAP 0x8000
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#define PCIXR_BRIDGE_STATUS 0x4
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#define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF
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#define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00
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#define PCIXM_BRIDGE_STATUS_64BIT 0x00010000
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#define PCIXM_BRIDGE_STATUS_133CAP 0x00020000
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#define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000
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#define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000
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#define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000
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#define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000
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#define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000
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#define PCIXM_BRIDGE_STATUS_266CAP 0x40000000
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#define PCIXM_BRIDGE_STATUS_533CAP 0x80000000
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/* HT (HyperTransport) Capability definitions */
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#define PCIR_HT_COMMAND 0x2
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