[ig4] We actually need to set the Rx threshold register one smaller.

Setting the IG4_REG_RX_TL register to 1 was actually generating an
interrupt after 2 bytes were available in the Rx fifo. We need to set the
register to 0 to get an interrupt for 1 byte already.

Obtained from:	DragonflyBSD (02f0bf2)

sys/dev/ichiic/ig4_iic.c

@@ -567,7 +567,7 @@ ig4iic_attach(ig4iic_softc_t *sc)
 	 *
 	 * See ig4_var.h for details on interrupt handler synchronization.
 	 */
-	reg_write(sc, IG4_REG_RX_TL, 1);
+	reg_write(sc, IG4_REG_RX_TL, 0);
 
 	reg_write(sc, IG4_REG_CTL,
 		  IG4_CTL_MASTER |