Pull in some suspend / resume changes from Intel's code
Tested by: mav@ MFC after: 3 days
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rnoland
parent
76f193cd69
commit
78db4b9606
@ -151,6 +151,8 @@ typedef struct drm_i915_private {
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u32 saveDSPACNTR;
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u32 saveDSPBCNTR;
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u32 saveDSPARB;
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u32 saveRENDERSTANDBY;
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u32 saveHWS;
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u32 savePIPEACONF;
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u32 savePIPEBCONF;
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u32 savePIPEASRC;
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@ -232,8 +234,8 @@ typedef struct drm_i915_private {
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u8 saveAR_INDEX;
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u8 saveAR[21];
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u8 saveDACMASK;
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u8 saveDACDATA[256*3]; /* 256 3-byte colors */
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u8 saveCR[37];
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struct {
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#ifdef __linux__
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struct drm_mm gtt_space;
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@ -651,7 +653,8 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
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#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
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(dev)->pci_device == 0x2E12 || \
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(dev)->pci_device == 0x2E22)
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(dev)->pci_device == 0x2E22 || \
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IS_GM45(dev))
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#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
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(dev)->pci_device == 0x29B2 || \
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@ -38,7 +38,7 @@ __FBSDID("$FreeBSD$");
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#define INTEL_GMCH_MEM_64M 0x1
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#define INTEL_GMCH_MEM_128M 0
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#define INTEL_855_GMCH_GMS_MASK (0x7 << 4)
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#define INTEL_GMCH_GMS_MASK (0xf << 4)
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#define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
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#define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
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#define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
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@ -48,6 +48,12 @@ __FBSDID("$FreeBSD$");
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#define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
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#define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
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#define INTEL_GMCH_GMS_STOLEN_128M (0x8 << 4)
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#define INTEL_GMCH_GMS_STOLEN_256M (0x9 << 4)
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#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
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#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
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#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
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#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
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/* PCI config space */
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@ -177,10 +183,28 @@ __FBSDID("$FreeBSD$");
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#define DISPLAY_PLANE_A (0<<20)
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#define DISPLAY_PLANE_B (1<<20)
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/*
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* Fence registers
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*/
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#define FENCE_REG_830_0 0x2000
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#define FENCE_REG_945_8 0x3000
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#define I830_FENCE_START_MASK 0x07f80000
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#define I830_FENCE_TILING_Y_SHIFT 12
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#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
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#define I830_FENCE_PITCH_SHIFT 4
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#define I830_FENCE_REG_VALID (1<<0)
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#define I915_FENCE_START_MASK 0x0ff00000
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#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
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#define FENCE_REG_965_0 0x03000
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#define I965_FENCE_PITCH_SHIFT 2
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#define I965_FENCE_TILING_Y_SHIFT 1
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#define I965_FENCE_REG_VALID (1<<0)
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/*
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* Instruction and interrupt control regs
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*/
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#define PRB0_TAIL 0x02030
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#define PRB0_HEAD 0x02034
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#define PRB0_START 0x02038
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@ -248,6 +272,7 @@ __FBSDID("$FreeBSD$");
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#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
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#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
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/*
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* Framebuffer compression (915+ only)
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*/
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@ -525,11 +550,17 @@ __FBSDID("$FreeBSD$");
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#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
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#define DCC_ADDRESSING_MODE_MASK (3 << 0)
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#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
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#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
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/** 965 MCH register controlling DRAM channel configuration */
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#define C0DRB3 0x10206
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#define C1DRB3 0x10606
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/** GM965 GM45 render standby register */
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#define MCHBAR_RENDER_STANDBY 0x111B8
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#define PEG_BAND_GAP_DATA 0x14d68
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/*
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* Overlay regs
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*/
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@ -593,6 +624,9 @@ __FBSDID("$FreeBSD$");
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/* Hotplug control (945+ only) */
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#define PORT_HOTPLUG_EN 0x61110
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#define HDMIB_HOTPLUG_INT_EN (1 << 29)
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#define HDMIC_HOTPLUG_INT_EN (1 << 28)
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#define HDMID_HOTPLUG_INT_EN (1 << 27)
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#define SDVOB_HOTPLUG_INT_EN (1 << 26)
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#define SDVOC_HOTPLUG_INT_EN (1 << 25)
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#define TV_HOTPLUG_INT_EN (1 << 18)
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@ -600,6 +634,9 @@ __FBSDID("$FreeBSD$");
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#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
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#define PORT_HOTPLUG_STAT 0x61114
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#define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
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#define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
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#define HDMID_HOTPLUG_INT_STATUS (1 << 27)
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#define CRT_HOTPLUG_INT_STATUS (1 << 11)
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#define TV_HOTPLUG_INT_STATUS (1 << 10)
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#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
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@ -629,7 +666,16 @@ __FBSDID("$FreeBSD$");
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#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
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#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
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#define SDVOC_GANG_MODE (1 << 16)
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#define SDVO_ENCODING_SDVO (0x0 << 10)
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#define SDVO_ENCODING_HDMI (0x2 << 10)
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/** Requird for HDMI operation */
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#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
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#define SDVO_BORDER_ENABLE (1 << 7)
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#define SDVO_AUDIO_ENABLE (1 << 6)
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/** New with 965, default is to be set */
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#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
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/** New with 965, default is to be set */
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#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
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#define SDVOB_PCIE_CONCURRENCY (1 << 3)
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#define SDVO_DETECTED (1 << 2)
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/* Bits to be preserved when writing */
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@ -1403,6 +1449,7 @@ __FBSDID("$FreeBSD$");
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#define PIPEB_FRMCOUNT_GM45 0x71040
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#define PIPEB_FLIPCOUNT_GM45 0x71044
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/* Display B control */
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#define DSPBCNTR 0x71180
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#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
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@ -125,11 +125,6 @@ static void i915_save_vga(struct drm_device *dev)
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/* VGA color palette registers */
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dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
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/* DACCRX automatically increments during read */
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I915_WRITE8(VGA_DACRX, 0);
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/* Read 3 bytes of color data from each index */
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for (i = 0; i < 256 * 3; i++)
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dev_priv->saveDACDATA[i] = I915_READ8(VGA_DACDATA);
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/* MSR bits */
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dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
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@ -231,12 +226,6 @@ static void i915_restore_vga(struct drm_device *dev)
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/* VGA color palette registers */
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I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
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/* DACCRX automatically increments during read */
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I915_WRITE8(VGA_DACWX, 0);
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/* Read 3 bytes of color data from each index */
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for (i = 0; i < 256 * 3; i++)
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I915_WRITE8(VGA_DACDATA, dev_priv->saveDACDATA[i]);
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}
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int i915_save_state(struct drm_device *dev)
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@ -250,6 +239,13 @@ int i915_save_state(struct drm_device *dev)
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pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
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#endif
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/* Render Standby */
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if (IS_I965G(dev) && IS_MOBILE(dev))
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dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
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/* Hardware status page */
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dev_priv->saveHWS = I915_READ(HWS_PGA);
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/* Display arbitration control */
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dev_priv->saveDSPARB = I915_READ(DSPARB);
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@ -379,6 +375,14 @@ int i915_restore_state(struct drm_device *dev)
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pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
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#endif
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/* Render Standby */
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if (IS_I965G(dev) && IS_MOBILE(dev))
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I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);
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/* Hardware status page */
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I915_WRITE(HWS_PGA, dev_priv->saveHWS);
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/* Display arbitration */
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I915_WRITE(DSPARB, dev_priv->saveDSPARB);
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/* Pipe & plane A info */
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