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Fix style(9).

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Pointed out by:	many
This commit is contained in:
Jung-uk Kim 2007-02-12 23:33:05 +00:00
parent f42a358a6f
commit 797b2220ae
4 changed files with 1810 additions and 1807 deletions
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28
sys/dev/bge/if_bge.c
View File

@ -1120,9 +1120,9 @@ bge_chipinit(struct bge_softc *sc)
/* Set up the PCI DMA control register. */
if (sc->bge_flags & BGE_FLAG_PCIE) {
/* PCI Express bus */
dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
(0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
(0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
BGE_PCIDMARWCTL_RD_WAT_SHIFT(0xf) |
BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x2);
} else if (sc->bge_flags & BGE_FLAG_PCIX) {
/* PCI-X bus */
if (BGE_IS_5714_FAMILY(sc)) {
@ -1140,14 +1140,14 @@ bge_chipinit(struct bge_softc *sc)
* The 5704 uses a different encoding of read/write
* watermarks.
*/
dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
(0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
(0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) |
BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3);
else
dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
(0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
(0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
(0x0F);
dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x3) |
BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3) |
0x0f;
/*
* 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
@ -1163,10 +1163,10 @@ bge_chipinit(struct bge_softc *sc)
}
} else
/* Conventional PCI bus */
dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
(0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
(0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
(0x0F);
dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) |
BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x7) |
0x0f;
if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
sc->bge_asicrev == BGE_ASICREV_BCM5704 ||

15
sys/dev/bge/if_bgereg.h
View File

@ -75,8 +75,6 @@
#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54
#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58
#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78
#define BGE_FW_DRV_ALIVE 0x00000001
#define BGE_FW_PAUSE 0x00000002
#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C
#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80
#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF
@ -87,6 +85,10 @@
#define BGE_SEND_RING_1_TO_4 0x00004000
#define BGE_SEND_RING_1_TO_4_END 0x00005FFF
/* Firmware interface */
#define BGE_FW_DRV_ALIVE 0x00000001
#define BGE_FW_PAUSE 0x00000002
/* Mappings for internal memory configuration */
#define BGE_STD_RX_RINGS 0x00006000
#define BGE_STD_RX_RINGS_END 0x00006FFF
@ -315,15 +317,16 @@
#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800
#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000
#define BGE_PCIDMARWCTL_RD_WAT 0x00070000
# define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16
#define BGE_PCIDMARWCTL_WR_WAT 0x00380000
# define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19
#define BGE_PCIDMARWCTL_USE_MRM 0x00400000
#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000
#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000
# define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24
#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000
# define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28
#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16)
#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19)
#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24)
#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28)
#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000
#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100

28
sys/dev/mii/brgphy.c
View File

@ -99,8 +99,8 @@ static void brgphy_reset(struct mii_softc *);
static void brgphy_loop(struct mii_softc *);
static void bcm5401_load_dspcode(struct mii_softc *);
static void bcm5411_load_dspcode(struct mii_softc *);
static void brgphy_fixup_adc_bug(struct mii_softc *);
static void brgphy_fixup_5704_a0_bug(struct mii_softc *);
static void brgphy_fixup_adc_bug(struct mii_softc *);
static void brgphy_fixup_adjust_trim(struct mii_softc *);
static void brgphy_fixup_ber_bug(struct mii_softc *);
static void brgphy_fixup_jitter_bug(struct mii_softc *);
@ -534,15 +534,14 @@ bcm5411_load_dspcode(struct mii_softc *sc)
}
static void
brgphy_fixup_adc_bug(struct mii_softc *sc)
brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
{
static const struct {
int reg;
uint16_t val;
} dspcode[] = {
{ BRGPHY_MII_AUXCTL, 0x0c00 },
{ BRGPHY_MII_DSP_ADDR_REG, 0x201f },
{ BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
{ 0x1c, 0x8d68 },
{ 0x1c, 0x8d68 },
{ 0, 0 },
};
int i;
@ -552,14 +551,15 @@ brgphy_fixup_adc_bug(struct mii_softc *sc)
}
static void
brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
brgphy_fixup_adc_bug(struct mii_softc *sc)
{
static const struct {
int reg;
u_int16_t val;
uint16_t val;
} dspcode[] = {
{ 0x1c, 0x8d68 },
{ 0x1c, 0x8d68 },
{ BRGPHY_MII_AUXCTL, 0x0c00 },
{ BRGPHY_MII_DSP_ADDR_REG, 0x201f },
{ BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
{ 0, 0 },
};
int i;
@ -593,7 +593,7 @@ brgphy_fixup_ber_bug(struct mii_softc *sc)
{
static const struct {
int reg;
u_int16_t val;
uint16_t val;
} dspcode[] = {
{ BRGPHY_MII_AUXCTL, 0x0c00 },
{ BRGPHY_MII_DSP_ADDR_REG, 0x000a },
@ -633,7 +633,7 @@ brgphy_fixup_jitter_bug(struct mii_softc *sc)
static void
brgphy_ethernet_wirespeed(struct mii_softc *sc)
{
u_int32_t val;
uint32_t val;
/* Enable Ethernet@WireSpeed. */
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
@ -645,7 +645,7 @@ static void
brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
{
struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
u_int32_t val;
uint32_t val;
/* Set or clear jumbo frame settings in the PHY. */
if (mtu > ETHER_MAX_LEN) {
@ -708,10 +708,10 @@ brgphy_reset(struct mii_softc *sc)
/* Handle any NetXtreme/bge workarounds. */
if (bge_sc) {
/* Fix up various bugs */
if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG)
brgphy_fixup_adc_bug(sc);
if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG)
brgphy_fixup_5704_a0_bug(sc);
if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG)
brgphy_fixup_adc_bug(sc);
if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM)
brgphy_fixup_adjust_trim(sc);
if (bge_sc->bge_flags & BGE_FLAG_BER_BUG)